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  s6j33 1 0 series s6j33 20 series s6j33 30 series s6j33 40 series 32- bit microcontroller spansion ? traveo tm family cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 - 1709 ? 408- 943 - 2600 document number: 002- 10635 rev.** revised march 4, 2016 preliminary the traveo family expands the companys automotive applications, scalability and high performance into one line - up and at the same time adds new features to fulfill the latest requirements of the automotive industry. based on the powerful arm ? cortex ? - r5f core in single operations, it offers state - of - the - art real time performance, safety and security features. the family supports the latest in - car networks and offers high perfo rmance graphics engines optimized for a minimum memory footprint and embeds dedicated features to increase data security in the car. s6j33 1 0 /20/30/40 is a microcontroller series for instrument clusters with small thin - film transistor (tft) displays. features ? system ? 32bit arm cortex - r5f cpu core at up to 240mhz ? general purpose i/o port : up to 146 ? 12- bit a/d converter : up to 48 channels ? external interrupt : up to 24 channels ? base timer : up to 32 channels ? 32- bit reload timer : up to 6 channels ? 32- bit free - run timer : 8 channels ? input capture unit : 12 channels ? output compare unit : 12 channels ? stepper motor controller (smc) : 6 units ? built - in cr oscillator ? real - time clock ? dma controller : 16 channels ? jtag debug interface ? graphics and display (optional) ? 2d graphic engine ? rgb888 ? lcd up to 4com x 32seg ? communication ? can - fd : up to 6 channels ? multi - function serial interface : up to 12 channels, selectable protocol : uart, csio, lin and i2c ? ethernet avb mac (optional) ? medialb (optional) ? automotive remote handler for apix ? (optional) ? memory ? hyperbus? memory interface ? ddr high speed spi ? exte r nal bus interface ? multimedia (optional) ? i2s input/output : 2 channels ? pcm to pwm output unit ? sound mixer : 1 unit x 10 inputs ? stereo audio dac ? security and safety ? secure hardware extension C she ? safety features, such as mpu, tpu, ecc and others ? crc generator : 1 channel ? watchdog timer with window function ? low voltage detector ? clock supervisor for all source clocks applications ? i nstrument cluster
document number: 002- 10635 rev.** page 2 of 247 s6j33 10/20/30/40 series preliminar table of contents features ................................................................................................................................................................................... 1 applications ............................................................................................................................................................................ 1 1. overview ............................................................................................................................................................................ 4 1.1 overview ....................................................................................................................................................................... 4 1.2 document definition ....................................................................................................................................................... 4 2. fun ction list ..................................................................................................................................................................... 5 2.1 product lineup ............................................................................................................................................................... 5 2.2 optional function ........................................................................................................................................................... 7 2.2.1 basic option ................................................................................................................................................................... 7 2.2.2 id ................................................................................................................................................................................... 7 2.2.3 restriction ...................................................................................................................................................................... 8 3. product description ........................................................................................................................................................ 10 3.1 overview ..................................................................................................................................................................... 10 3.2 product desc ription ...................................................................................................................................................... 10 3.2.1 ethernet ....................................................................................................................................................................... 15 4. package and pin assignment ........................................................................................................................................ 16 4.1 pin assignment ........................................................................................................................................................... 16 4.1.1 teqfp - 208 pin assignment(S6J3310) ........................................................................................................................ 16 4.1.2 teqfp - 176 pin assignment(S6J3310) ........................................................................................................................ 17 4.1.3 teqfp - 144 pin assignment(S6J3310) ........................................................................................................................ 18 4.2 package dimensions ................................................................................................................................................... 19 4.2.1 teqfp208 ................................................................................................................................................................... 19 4.2.2 teqfp176 ................................................................................................................................................................... 20 4.2.3 teqfp144 ................................................................................................................................................................... 21 5. io circuit type ................................................................................................................................................................. 23 5.1 i/o circuit type ........................................................................................................................................................... 23 5.2 note ............................................................................................................................................................................. 28 6. port description .............................................................................................................................................................. 29 6.1 port description list ...................................................................................................................................................... 29 6. 2 remark ........................................................................................................................................................................ 50 7. port configuration .......................................................................................................................................................... 51 7.1 resource input configuration module ......................................................................................................................... 51 7.1.1 ric(S6J3310) .............................................................................................................................................................. 51 7.2 port output function configuration ........................................................................................................................... 143 7.2.1 standard configuration(S6J3310) .............................................................................................................................. 143 8. precautions and handling devices ............................................................................................................................. 154 8.1 handling precautions ................................................................................................................................................ 154 8.1.1 precautions for product design .................................................................................................................................. 154 8.1.2 precautions for package mounting ............................................................................................................................ 155 8.1.3 precautions for use environment ............................................................................................................................... 156 8.2 handling devices ...................................................................................................................................................... 157 9. electric characteristics ................................................................................................................................................ 159 9.1 electrical characteristics ........................................................................................................................................... 159 9.1.1 absolute maximum rating ......................................................................................................................................... 159 9.1.2 recommended operating condition ............................................................................................................................ 162 9.1.3 dc characteristics ...................................................................................................................................................... 164
document number: 002- 10635 rev.** page 3 of 247 s6j33 10/20/30/40 series preliminar 9.1.4 ac characteristics ...................................................................................................................................................... 173 9.1.5 a/d converter ............................................................................................................................................................. 235 9.1.6 audio dac ................................................................................................................................................................. 239 9.1.7 flash memory .......................................................................................................................................................... 242 10. abbreviation .................................................................................................................................................................. 243 11. ordering information .................................................................................................................................................... 245 document history ............................................................................................................................................................... 246 sales, sol utions, and legal information ........................................................................................................................... 247
document number: 002- 10635 rev.** page 4 of 247 s6j33 10/20/30/40 series preliminar 1. overview 1.1 overview s6j33 1 0 /20/30/40 is a microcontroller series which is to be applied to automotive systems representative of a graphical cluster control unit on a dashboard. 1.2 document definition the related documents of s6j33 10/20/30/40 are the followings. table 1 -1 document type definition primary user document code S6J3310/20/30/40 datasheet the function and its characteristics are specified quantitatively. investigator and hardware engineer 002- 10635 s6j3300 hardware manual the function and its operation of s6j3300 series are described. software engineer 002- 10185 traveo tm platform hardware manual the function and its operation of cpu core platform are described. software engineer 002- 07884 application note the reference software, sample application, the reference board design and so on are explained. 6zddqg hardware engineer under consideration ote s ? refer all documents for the system development. ? "primary user" is a most likely engineer for whom the document is the most useful. ? the description of the datasheet and the s6j3300 hardware manual should prece de the duplicated description of traveo tm p latform hardware manual. ? traveo tm p latform hardware manual is expected to be used as dictionary of platform specification.
document number: 002- 10635 rev.** page 5 of 247 s6j33 10/20/30/40 series preliminar 2. function list 2.1 product lineup the table shows the functions which are implemented in s6j33 1 0 /20/30/40 series. table 2 -1 function S6J3310 s6j3320 s6j3330 s6j3340 remark cpu core arm cortex r5f fpu available ppu available mpu available tpu available endian little endian core clock frequency 240mhz hpm bus frequency 2 0 0 mhz llpm bus frequency 240 mhz resource clock frequency 80mhz (max) embedded cr oscillation slow clock:100khz, fast clock: 4mhz (center frequency) 9.1.4.1 pll pll0, 1, 2, 3 sscg pll sscg0, 1, 2, 3 clock supervisor available dma 16 ch boot rom 16 kbyte jtag available data cache 16kbyte instruction cache 16kbyte program flash option 2.2.1 work flash 112kbyte tcram 128kbyte ram 384kbyte backup ram 32kbyte security (she) option low latency interrupt available power domain 5 domains external power supply 5v (vcc5, vcc53) 3v (vcc3, vcc53) , 1. 2v (vcc12) embedded ldo power supply for 5.0v available low voltage detection of external power supply available low voltage detection of internal ldo output available hardware watchdog timer available software watchdog timer available package option 2.2.1 autosar autosar 4.0.3 general purpose i/o option 2.2.2 up/down counter 2 ch i/o timer (frt 5ch x icu 6ch x ocu 6ch) + (frt 3ch x icu 6ch x ocu 6ch) 32bit reload timer 6 ch real time clock available automatic calibration sound generator 5 ch sound waveform generator 1 unit x 5 outputs see 2.2.1 sound mixer 1 unit x 10 inputs no 2.2.1 stereo audio dac 1 unit (l and r) no 2.2.1
document number: 002- 10635 rev.** page 6 of 247 s6j33 10/20/30/40 series preliminar function S6J3310 s6j3320 s6j3330 s6j3340 remark pcm - pwm 1 unit (l and r) no see 2.2.1 base timer 16 units (32 ch) stepping motor controller (smc) for 6 gauges 12bit a/d converter 2 unit 48 input ports (max) 2.2.2 crc 1 unit programmable crc 1 unit source clock timer 4 ch nmi available external interrupt 24 ch internal interrupt 512 vectors i2s 2 ch one only supports an output as a function of the sound system. 663, f sdg63, s6 1 ch see the ac specification on 9.1.4.17 . l - qflqldlqdf f - fd f - ssg f ,tlydq 2 desfdqqg ethernet avb 1 unit no 2.2.1 media lb (most50) 1 unit no 2.2.1 lcd controller 4com x 32 seg (max) 2.2.2 indicator pwm 1 ch mpu for ahb 1 unit mpu for axi 1 unit graphic engine clock 8 0mhz (max) graphic axi clock 80 mhz (max) display clock 25 mhz display clock source graphic display controller clock or external clock target resolution wqvga 480 x 272 target frame rate 60 fps number of display outputs 1 output ttl output (rgb888) option 2.2.1 2d graphic engine 1 unit 2d driver api spansion proprietary external bus 1 ch apix for arh (automotive remote handler) 1 unit (2 ch) no see 2.2.1 ote s ? the options are described in 2.2 .
document number: 002- 10635 rev.** page 7 of 247 s6j33 10/20/30/40 series preliminar 2.2 optional function 2.2.1 basic option the figure shows the optional function and the part number relations of the series. figure 2 - 1 ote s ? this table only shows the relations between the optional function and the part numbers. that is, all products are not necessarily available for orders. see 11 , and confirm actual availabilities of products. ? the sound system is composed of the sound waveform generator, the sound mixer, the audio dac, pcm - pwm, and i2s0. 222 d id is specified for each function digit and revision which is defined at figure 2 -1. function digit revision chip id jtag id s,u ,t,v b 0x 1 0120000 0x1000b5cf a,c b 0x 1 012a000 0x1000b5cf b,d ,f,h b 0x 1 0122000 0x1000b5cf j 3 3 x x x x x x x x x x x x ordering options 7 digit revision : revision version option : * chip erase enable register pin count : memory size : function : product series identifier : automotive mcu 3v fixed to enable selectable dvcc 5v 3v 3v 5v 3v 3v 5v 3v 3v 5v 3v b u off 5v c digit graphic ethernet medialb sound system arh for apix 4 5v pin count off h 144pin 112kb 512kb 4,160kb 112kb 512kb k 208pin b 1,600kb j 176pin 3,136kb 112kb 512kb 16+16kb c 2,112kb 112kb 512kb 16+16kb 16+16kb 1 vcc 5v digit she mk_ceer* on on 5v a v h digit 16+16kb digit flash ram program work backup
document number: 002- 10635 rev.** page 8 of 247 s6j33 10/20/30/40 series preliminar 2.2.3 restriction some functions have restrictions which depend on package pin counts. table 2 -2 function teqfp176 teqfp144 analog input port (12bit - adc) - an 4 ~7, an10~11, an14~15, an19~20, an22~23, an25~ 30 , an33~ 8 , an48 seg port of lcd controller - seg0~3 seg5~8 general purpose i/o p4_00 ~ p4_31 p4_00 ~ p4_31 p3_00 ~ p3_31 can rx0_2, tx0_2 rx1_0, tx1_0 rx1_1, tx1_1 rx2_0, tx2_0 rx2_1, tx2_1 rx3_ 2 , tx3_ 2 rx0_1, tx0_1 rx0_2, tx0_2 rx1_0, tx1_0 rx1_1, tx1_1 rx2_0, tx2_0 rx2_1, tx2_1 rx3_1, tx3_1 rx3_ 2 , tx3_ 2 rx5_1, tx5_1 rx6_1, tx6_1 basetimer - ppg4/5/6/7/8/9_tout0_1 ppg4/5/6/7/8/9_tout2_1 ppg10/11/12/13/15_tout0_1 ppg10/11/12/13/14/15_tout2_1 ppg0/1/2/3/4/5_tin1_1 ppg6/7/8/9/10/11_tin1_1 ppg12/13/14/15_tin 1 _1 extbus - mdqm1 mad15~21 mdata8~15
document number: 002- 10635 rev.** page 9 of 247 s6j33 10/20/30/40 series preliminar function teqfp176 teqfp144 external interrupt eint1_4, eint1_5 eint2_1, eint2_ 2 eint3_2, eint4_2 eint5_4, eint5_5 eint6_4, eint7_1 eint7_4, eint8_4 eint8_5, eint9_1 eint10_1, eint10_4 eint10_5, eint13_2 eint13_3, eint14_2 eint14_3, eint15_3 eint16_1, eint16_3 eint16_4, eint19_4 eint20_3, eint21_3 eint22_1, eint22_3 eint23_3, eint23_4 eint0_4, eint1_1 eint1_4, eint1_5 eint2_1, eint2_2 eint2_4, eint3_1 eint3_2, eint3_4 eint4_2, eint4_4 eint5_4, eint5_5 eint6_1, eint6_4 eint7_1, eint7_4 eint8_1, eint8_4 eint8_5, eint9_1 eint9_2, eint10_1 eint10_2, eint10_4 eint10_5, eint11_2 eint11_5, eint12_1 eint12_2, eint12_5 eint13_2, eint13_3 eint13_5, eint14_1 eint14_2, eint14_3 eint14_5, eint15_2 eint15_3, eint16_1 eint16_2, eint16_3 eint16_4, eint16_5 eint17_1, eint17_3 eint17_5, eint18_1 eint18_3, eint18_5 eint19_1, eint19_3 eint19_4, eint20_1 eint20_2, eint20_3 eint21_1, eint21_3 eint22_1, eint22_3 eint23_3, eint23_4 ? see multiplexed functions on pin assignment sheet. ? the optional restriction will be added without notification.
document number: 002- 10635 rev.** page 10 of 247 s6j33 10/20/30/40 series preliminar 3. product description 3.1 overview this chapter explains the product features of s6j33 1 0 /20/30/40 series. the description of this chapter should precede the duplicated description on traveo tm platform hardware manual . 3.2 product description the table shows features. table 3 -1 feature description technology 40nm cmos technology with embedded flash fully automotive qualified according to iso/ts 16949 and aec - q100 developed according to iso26262, safety target asil -b functional safety the product series has some functional safety features suited for asil b application. peripherals see function list. power domain (pd) see the traveo tm platform hardware manual and chapter state transition in detail. the product series supports the power off control of pd1, pd2 (including pd3 and 5), and pd6. the power domain resets of pd3 and pd5 included in pd2 are not supported in the product series, and "0" is always read from the reset factor flags of them. this series doesn't support partial wakeup for pd6. debug and trace see the platform hardware manual in detail. ? standard 5 - pin jtag interface ? 4kb embedded trace buffer 4 - bit trace support for teqfp package. system control see the platform hardware manual in detail. main and sub oscillator is available. ? a wide range of 3.6 - 4mhz is available for main oscillator ? 32khz is available for sub oscillator sub clock is enable/disable by register settings clock see the platform hardware manual in detail. clk_clko (clock output function) is supported. clock supervisor see the platform hardware manual in detail. this product series doesnt support clock supervisor output port. (related register and internal circuit is implemented.) based on cortex r5f platform following resets are not mounted on this device. ? initx ? srstx hardware watchdog see the traveo tm platform hardware manual in detail. hardware watchdog function stops during pss mode. in the related register of hwdg_cfg, the bit allowstopclk is always read as 1 (hwdg_cfg.allowstopclk=1). the product series doesnt support watchdog counter monitor o utput port. (related register and internal circuit is implemented.)
document number: 002- 10635 rev.** page 11 of 247 s6j33 10/20/30/40 series preliminar feature description standby mode see the platform hardware manual in detail. standby mode with 5v (or 3v) single external power supply is available. turning off the 1. 2v external power supply in st andby mode is available. the long term pulse of the indicator pwm can be outputted during rtc standby mode. pll / sscg pll see the platform hardware manual in detail. use case assumption is following. pll ? sound system clock ? sound frequency master clock ? peripherals ? display clock ? trace clock sscg ? cpu core ? gdc core ? hyper bus ? ddr- hsspi down spread mode is only supported and available. external interrupts see the platform hardware manual in detail. nmi see the platform hardware manual in detail. 1 nmi pin. memory protection mpu16 ahb: see the platform hardware manual in detail. mpu for axi: ch.0 mpu for ahb: ch.1 additional mpu for graphic sub system, medialb and ethernet avb. they are described on the chapter of mpu for ahb and mpu for axi to configure lock or unlock for both mpuxn_unlock and mpuhn_unlock, ? lock: 0x112abb56 ? unlock: 0xaccabb56 peripheral protection see the platform hardware manual in detail. protected peripherals are described in the base address map. internal memories ram 384kbyte 1 wait cycle is necessary for ram read at over 120mhz. internal memories tcram 128kbyte internal memories backup ram 32kbyte backup ram can only be operated in run mode (normal operation mode). in other mode the memory content should be retained, but it cannot be operated. sleep control for b a ckup ram is not supported and cannot be used.
document number: 002- 10635 rev.** page 12 of 247 s6j33 10/20/30/40 series preliminar feature description embedded program/work flash memory embed ded program flash can be accessed with 0 wait cycle if cpu frequency is 80mhz or less. 0 - wait - cycle: 80mhz or less. 1 - wait - cycle: 160mhz or less. 2 - wait - cycle: more than 160mhz. work flash can be accessed with 0 - wait - cycle if cpu frequency is 12.5 mhz or less. 7 - wait - cycle: 80mhz or less. 1 3 - wait - cycle: 160mhz or less. t he wait - cycle setting see the traveo tm platform hardware manual in details . the clk_fclk maximum frequency should be referred in 9.1.4.3 . erase suspend is supported. reading and writing to the other sector are possible when flash erase is suspended. serial flash programing and parallel flash programing are supported. margin mode is not supp orted. internal power domain pd1: always on pd2: cortex r5f platform/ gdc/ additional peripherals pd4: backup ram in always on domain pd6: peripherals in always on domain * the chapter of the block diagram explains in detail. power supply 5v, and 3v, 1. 2v external power supply is required. built in ldo provides internal power supply for always on region (pd1). 1.2v external power supply control pin is supported. 3v external power supply should be controlled by gpio. there are constraints of power on/of f sequence. low voltage detection lvd for external voltage is supported. lvd for internal voltage is supported. see 9.1.4.11 and 9.1.4.12 . low voltage detection for ram retention (rvd) rvd for ram retention is effective during the standby mode only. that is, it is only for the backup ram of 32kb that the function is avail able. resource inter - connect the output signal of some resources can be inputted to the other resource. i/o ports 5v general purpose i/o 3v general purpose i/o multi input level and multi output drivability pull - up, pull - down function is available. resource input and output is multiplexed. +b input is allowed many pins of 3.3v, 5v and 3.3v/5v i/o domain. a/d converter 12bit resolution, 2 unit 48 channels of analog input for teqfp208 48 channels of analog input for teqfp176 35 channel of analog inp ut for teqfp144 24 channels of them are shared with the smc for teqfp208/176/144 external trigger and timer trigger are available. the description of the a/d converter function should be referred in the s6j3300 hardware manual. though the chapter of i/o po rt in traveo tm platform hardware manual describes another a/d converter function, do not refer it. crc see the platform hardware manual in detail.
document number: 002- 10635 rev.** page 13 of 247 s6j33 10/20/30/40 series preliminar feature description programmable crc dma support sound generator produces sound/melody with varying frequency and amplitude for convenient duration square wave sound output automatic linear amplitude increment or decrement interrupt request generated when specified sound length has ended sound waveform generator sine waveform, saw tooth waveform and square wavefor m are generated with easy configuration of the parameters which specified sound sources. fade - in and fade- out control for reverberation. sound mixer the input channels of 0 4 are reserved for waveform generator. mixing different sampling frequency sou nds. mixing internal sounds and external i2s input sounds. saturating addition function for keeping sound quality. cut a specific frequency data by digital filter. lpf is support by fir filter. fade - in and fade- out control. pcm - pwm conversion of pcm audio streaming to pulse width modulated signals. supports 2 output channels for stereo and mono data up to 16 - bit output sample resolution support for half and full h - bridges audio dac the sound source of the fixed 48khz sampling frequency can be output ted. 1unit, l/r channels support. btl connection is available. i2s 2ch. ? i2s0 only supports the output of sound sources. ? i2s1 supports both the input and the output. ? i2s has its own ppu, but the function is fixed to disable. base timer see the platform hardware manual in detail. a unit consists of a pair of 16bit base timers. 16 units, that is, 32 channels of base timers are available. dgl see the platform hardware manual in detail. i/o timer see the platform hardware manual in detail. up/down counter see the platform hardware manual in detail. multi - functional serial (mfs) see the platform hardware manual in detail. ports of mfs have the dedicated i/o for i2c. see port des cription list in detail. when the voltage supply of i2c interface is 5.0v, it isn't able to use the i/o cells of 3.3v voltage supply for the i2c terminal. - fd flexible data rate is supported. 16kb/ch of message ram is available. the clock output from can pre - scaler is supplied to every can. ecc error generation function of the message ram is not supported for this device. therefore can fd ecc error insertion control register (fdfecr) is not writeable. dlf zld - calibration 6 traveo tm 3ddgzddqd lqgdl l6sg63, ch.0: hsspi as a mcu peripheral
document number: 002- 10635 rev.** page 14 of 247 s6j33 10/20/30/40 series preliminar feature description hyper bus i/f ch.0: hyper bus as a mcu peripheral the following register is not supported and cannot be used. ? controller status register (hyperbusin _csr) ? interrupt status register (hyperbusin_isr) ? write protection register (hyperbusin_wpr) ? test register (hyperbusin_test) gpo signal can only be used for "internal control example by gpo" in this product, that is, it can select using hyperbus of pf or us ing hyperbus of graphic sub system. 6ssq 6 dffdqqdglyzllsfdsdell qd,qsds ql, 6 traveo tm 3ddgzddqd lqgdl q 10/100 mbps mii - interface supports audio - video bridging (avb) medialb most50 (1024fs) 3 wires maximum 15ch is available. lcd controller teqfp208 : 4com x 32seg teqfp176 : 4com x 32seg teqfp144 : 4com x 24seg lcdc pins are initialized with reset. (stop lcdc alternating current output) duty and static of segment output is supported. (seg23/st0, seg24/st1, seg25/st2, seg26/st3, seg27/st4, seg28/st5, seg29/st6, seg30/st7, seg31/st8) 6 6 traveo tm 3ddgzddqd lqgdl 6ffl se e the platform hardware manual in detail. graphics subsystem 200 mhz maximum clock frequency variable setting about gdc clock. (asynchronous with cpu clock) 480 x 272 pixels maximum frame resolution video modes up to 50 mhz pixel clock rgb888, order replacement of rgb pins. external bus teqfp208 : 22bit address and 16 bit data teqfp176 : 22bit address and 16 bit data teqfp144 : 15bit address and 8 bit data arh 2 ch this device does not have phy macro and its function. ? the description of the preliminary documentation will be changed without any notification.
document number: 002- 10635 rev.** page 15 of 247 s6j33 10/20/30/40 series preliminar 3.2.1 ethernet the following functions are not supported. functions remark direct memory access interface. - partial store and forward - force max amba burst tx/rc - priority que ueing (screening) external fifo interface additional low latency tx fifo interface for dma configurations mac transmit block - half - duplex - collision - back_pressure mac filtering block - external address match - vlan tag - wakeup on lan ieee 1588 and ieee 802.1as support mac pfc priority based pause frame support energy efficient ethernet support lpi operation in cadence ip 802.1qav support C credit based shaping phy interface - gmii - sgmii - tbi 10/100/1000 operation - 10 m - 1000 m sgmii operation jumbo frames physical control sub - layer
document number: 002- 10635 rev.** page 16 of 247 s6j33 10/20/30/40 series preliminar 4. package and pin assignment 4.1 pin assignment alphabets with pin numbers are signs specify i/o circuit type. teqf - 2 in ssinment s633 figure 4 - 1 : teqfp -208 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - lcdd4 lcdd3 lcdd0 scs43_0 scs42_0 lcdd2 lcdd1 sda4 scl4 scs32_1 scs31_1 scs23_1 scs22_1 scs21_1 scs20_1 sot2_1 scl12 sda11 scl11 sda10 scl10 sda9 scs41_0 scs40_0 sot4_0 sck4_0 sin4_0 scs33_1 eint20_5 eint19_5 scs30_1 sot3_1 sck3_1 sin3_1 ppg14_tout0_1 ppg13_tout2_1 ppg13_tout0_1 ppg12_tout2_1 ppg12_tout0_1 sda12 sck12_0 sin12_0 scs111_0 scs110_0 sot11_0 sck11_0 sin11_0 scs100_0 sot10_0 sck10_0 sin10_0 scs91_0 scs90_0 sot9_0 eint3_6 eint2_6 eint1_6 eint0_6 eint23_5 eint22_5 eint0_0 eint21_5 adtrg1_2 adtrg0_1 ppg12/13/14/15_tin1_1 ppg15_tout2_1 ppg15_tout0_1 ppg14_tout2_1 eint15_5 eint14_5 eint13_5 eint12_5 eint11_5 scs120_0 sot12_0 ppg12/13/14/15_tin1_0 ppg15_tout2_0 ppg15_tout0_0 ppg14_tout2_0 ppg14_tout0_0 ppg13_tout2_0 ppg13_tout0_0 ppg12_tout2_0 ppg12_tout0_0 ppg6/7/8/9/10/11_tin1_0 ppg11_tout2_0 ppg11_tout0_0 ppg10_tout2_0 ppg10_tout0_0 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 eint18_5 eint17_5 eint16_5 eint3_1 seg4 seg1 seg0 sck2_1 sin2_1 eint9_5 eint7_5 eint6_5 eint23_0 eint4_5 eint3_5 eint2_5 eint0_5 eint22_0 eint22_4 eint21_4 eint20_4 eint21_0 eint18_4 eint17_4 eint15_4 mad0 mdata7 mdata6 mdata5 mdata4 mdata3 mdata2 mdata1 mdata0 mcsx1 seg8 seg7 seg5 mcsx0 mdata11 mdata10 mdata9 mdata8 pwm2m5 pwm2p5 pwm1m5 pwm1p5 pwm2m4 pwm2p4 pwm1m4 pwm1p4 pwm2m3 pwm2p3 pwm1m3 pwm1p3 pwm2m2 pwm2p2 pwm1m2 eint16_4 pwm1p2 dsp0_r6_0 dsp0_r5_0 dsp0_r4_0 dsp0_r3_0 dsp0_r2_0 dsp0_r1_0 dsp0_r0_0 dsp0_clk_0 dsp0_vsync_0 dsp0_hsync_0 mdata15 mdata14 mdata13 mdata12 dsp0_en_0 i2s0_sck_1 i2s0_ws_1 i2s0_sd_1 i2s0_eclk_1 eint10_5 eint2_1 an63 eint8_5 an62 an61 an60 eint5_5 an59 an58 an57 eint1_5 an56 an55 eint23_4 an54 an53 an52 eint19_4 an51 an50 an49 an47 vss p2_19 p2_18 p2_17 p2_16 p2_15 p2_14 p2_13 p2_12 p2_11 p2_10 p3_31 p3_30 p3_29 p3_28 vcc53 vss vcc12 p2_09 p3_27 p3_26 p3_25 p3_24 p4_31 p4_30 dvcc dvss p2_08 p4_29 p2_07 p2_06 p2_05 p4_28 p2_04 p2_03 p2_02 p4_27 p2_01 dvcc dvss p2_00 p4_26 p1_31 p1_30 p1_29 p4_25 p1_28 p1_27 p1_26 p4_24 p1_25 dvcc p p p p p p p p p p p p p p p p p 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 vcc53 - 1 156 - dvss - - - - - - - - - - - - - - - - - - - - - lcdd5 eint0_1 seg19 mad 1 dsp0_r7_0 p0_00 s 2 155 p p1_24 an46 pw m2m1 eint14_4 ppg9_tout2_0 sck9_0 scl9 - - - - - - - - - - - - lcdd6 arh0_aic1_tcki arh0_aic1_dnclk sin1_0 eint1_0 seg20 mad 2 dsp0_g0_0 p0_01 s 3 154 p p1_23 an45 pwm2p1 eint20_0 ppg9_tout0_0 sin9_0 - - - - - - - - - - - - lcdd7 arh0_aic1_dndata1 arh0_aic1_tda1 scl1 sck1_0 eint4_1 seg21 mad 3 dsp0_g1_0 p0_02 s 4 153 p p1_22 an44 pw m1m1 eint13_4 ppg8_tout2_0 tx6_0 scs80_0 - - - - - - - - - - - - lcdd8 arh0_aic1_dbg_out_1 sda1 sot1_0 eint5_1 seg22 mad 4 dsp0_g2_0 p0_03 s 5 152 p p1_21 an43 pwm1p1 eint19_0 ppg8_tout0_0 rx6_0 sot8_0 sda8 - - - - - - - - - - - - - - - rx0_2 - eint7_1 rxclk_1 p4_00 t 6 151 p p1_20 an42 pw m2m0 eint12_4 ppg7_tout2_0 sck8_0 scl8 - - - - - - - - - - - - - - - - tx0_2 - eint9_1 rxer_1 p4_01 t 7 150 p p1_19 an41 pwm2p0 eint18_0 ppg7_tout0_0 sin8_0 - - - - - - - - - - - - - - - - - - - eint10_1 rxdv_1 p4_02 t 8 149 p p1_18 an40 pw m1m0 eint11_4 ppg6_tout2_0 tx5_0 scs171_0 - - - - - - - - - - - - lcdd9 arh0_aic1_dbg_out_0 sin0_1 scs10_0 eint11_1 seg23 mad 5 dsp0_g3_0 p0_04 s 9 148 p p1_17 an39 pwm1p0 eint17_0 ppg6_tout0_0 rx5_0 scs170_0 - - - - - - - - - - - lcdd10 arh0_aic1_dndata0 arh0_aic1_tda0 sot0_1 scs11_0 eint13_1 seg24 mad 6 dsp0_g4_0 p0_05 s 10 147 - dvcc - - - - - - - - - - - - - - - lcdd11 arh0_aic1_upclk arh0_aic1_rck sck0_1 scs12_0 ppg0_tout0_1 eint15_1 seg25 mad 7 dsp0_g5_0 i2s1_eclk_0 p0_06 s 11 146 - dvss - - - - - - - - - - - - - - - lcdd12 arh0_aic1_updata1 arh0_aic1_rda1 scs00_1 scs13_0 ppg0_tout2_1 eint23_1 seg26 mad 8 dsp0_g6_0 i2s1_sd_0 p0_07 s 12 145 - avss - - - - - - - - - - - - - - - - - lcdd13 arh0_aic1_updata0 arh0_aic1_rda0 ppg1_tout0_1 eint0_2 seg27 mad 9 dsp0_g7_0 i2s1_ws_0 p0_08 s 13 144 - avrl5 - - - - - - - - - - - - - - - - lcdd14 arh0_aic0_tcki arh0_aic0_dnclk sin17_1 ppg1_tout2_1 eint1_2 seg28 mad 10 dsp0_b0_0 i2s1_sck_0 p0_09 s 14 143 - avrh5 - - - - - - - - - - - - - - - - - - - - - scs170_1 rx3_2 - eint2_2 txclk_1 p4_03 t 15 142 - avcc5 - - - - - - - - - - - - - - - - - - - - - sck17_1 tx3_2 - eint3_2 txen_1 p4_04 t 16 141 g p4_23 - eint10_4 - - scs160_1 - - - - - - - - - - - - - - - - - sot17_1 - eint4_2 txd0_1 p4_05 t 17 140 e p4_22 adtrg1_0 eint22_1 - - scs161_1 - - - - - - - - - - - lcdd15 arh0_aic0_dndata1 arh0_aic0_tda1 scs171_1 ppg2_tout0_1 eint5_2 seg29 mad 11 dsp0_b1_0 i2s0_eclk_0 p0_10 s 18 139 h p1_16 adtrg0_0 - eint9_4 sgo4_0 ppg0/1/2/3/4/5_tin1_0 ocu10_otd1_0 tot49_0 sot17_0 sda17 wot sysc0_clk_0 - - - - - - - lcdd16 arh0_aic0_dbg_out_1 ppg2_tout2_1 eint6_2 seg30 mad 12 dsp0_b2_0 i2s0_sd_0 p0_11 s 19 138 g p4_21 - eint8_4 - sck16_1 - - - - - - - - - - - - - - lcdd17 arh0_aic0_dbg_out_0 ppg3_tout0_1 eint7_2 seg31 mad 13 dsp0_b3_0 i2s0_ws_0 p0_12 s 20 137 g p4_20 - eint7_4 - - sot16_1 - - - - - - - - - - - - - cs# arh0_aic0_dbg_select ppg3_tout2_1 eint8_2 c o m0 mad 14 dsp0_b4_0 i2s0_sck_0 p0_13 s 21 136 g p4_19 - eint16_1 - - sin16_1 - - - - - - - - - - - - - - - - - - - - - vcc53 - 22 135 - vcc5 - - - - - - - - - - - - - - - - - - - - - - - - - - vss - 23 134 - vss - - - - - - - - - - - - - - - - - - - - - - - - - - vcc12 - 24 133 - vcc12 - - - - - - - - - - - - - - - - - - - - - sin1_1 ppg4_tout0_1 eint1_1 mad 15 txd1_1 p3_00 t 25 132 - vcc12 - - - - - - - - - - - - - - - - - - - - - sck1_1 ppg4_tout2_1 eint9_2 mad 16 txd2_1 p3_01 t 26 131 g p4_18 - eint6_4 - sin12_1 - - - - - - - - - - - - - - - - - sot1_1 ppg5_tout0_1 eint10_2 mad 17 txd3_1 p3_02 t 27 130 g p4_17 - eint5_4 - sot12_1 - - - - - - - - - - - - - - - - - scs10_1 ppg5_tout2_1 eint11_2 mad 18 txer_1 p3_03 t 28 129 h p1_15 an32 eint16_0 sga4_0 ppg5_tout2_0 ocu10_otd0_0 icu10_in1_0 tin49_0 sck17_0 sck12_1 scl17 indicator0_1 - - - - - - - - - - scs11_1 ppg0/1/2/3/4/5_tin1_1 eint12_2 mad 19 rxd0_1 p3_04 t 29 128 g p1_14 an31 eint15_0 sgo3_0 ppg5_tout0_0 ocu9_otd1_0 icu10_in0_0 tot48_0 tx3_0 sin17_0 sysc0_clk_1 - - - - - - - - - - - - - - eint13_2 rxd1_1 p4_06 t 30 127 g p3_23 an30 eint4_4 tx6_1 scs120_1 - - - - - - - - - - - - - - - - - - - - eint14_2 rxd2_1 p4_07 t 31 126 g p3_22 an29 eint19_1 rx6_1 scs91_1 - - - - - - - - - - - - - - - - - scs12_1 sin4_1 eint15_2 mad 20 rxd3_1 p3_05 t 32 125 g p3_21 an28 eint3_4 tot49_1 scs90_1 - - - - - - - - - - - - - - - - - scs13_1 sot4_1 eint16_2 mad 21 md io _1 p3_06 t 33 124 e p3_20 eint2_4 ppg6/7/8/9/10/11_tin1_1 tin49_1 tx5_1 sot9_1 - - - - - - - - - - - - - - wr# arh0_aic1_dbg_select sck4_1 eint17_2 c o m1 mo ex dsp0_b5_0 p0_14 s 34 123 e p3_19 eint17_1 ppg11_tout2_1 ocu10_otd1_1 icu10_in1_1 rx5_1 sck9_1 - - - - - - - - - - - - - - rd# scs40_1 eint18_2 c o m2 mw ex dsp0_b6_0 p0_15 s 35 122 e p3_18 eint20_1 ppg11_tout0_1 ocu10_otd0_1 icu10_in0_1 sin9_1 - - - - - - - - - - - - - - arh0_aic0_dndata0 arh0_aic0_tda0 scs41_1 eint19_2 c o m3 mc lk dsp0_b7_1 p0_16 s 36 121 - vss - - - - - - - - - - - - - - - - - - - - - - - scs42_1 eint20_2 md q m1 p3_07 t 37 120 - c - - - - - - - - - - - - - - - - - - - - scs43_1 eint21_2 v0 md q m0 dsp0_b7_0 rxclk_0 p0_17 v 38 119 o mo d e - - - - - - - - - - - - - - - - - - rs arh0_aic0_upclk arh0_aic0_rck eint22_2 v1 mc sx2 mdc_1 rxer_0 p0_18 v 39 118 d psc_1 - - - - - - - - - - - - - - - - - - res# arh0_aic0_updata1 arh0_aic0_rda1 eint23_2 v2 mc sx3 col_1 rxdv_0 p0_19 v 40 117 n rstx - - - - - - - - - - - - - - - - - - te arh0_aic0_updata0 arh0_aic0_rda0 eint0_3 v3 mrdy crs_1 txclk_0 p0_20 u 41 116 g p4_16 - eint1_4 - - - - - - - - - - - - - - - - - - - - - - - - vcc53 - 42 115 g p3_17 an26 eint0_4 sgo4_1 ppg10_tout2_1 ocu9_otd1_1 icu9_in1_1 tot48_1 tx3_1 - - - - - - - - - - - - - - - - - - vss - 43 114 g p3_16 an25 eint14_1 sga4_1 ppg10_tout0_1 ocu9_otd0_1 icu9_in0_1 tin48_1 rx3_1 - - - - - - - - - - - - - - - - - - avss - 44 113 g p1_13 an24 eint14_0 sga3_0 ocu9_otd0_0 tin48_0 rx3_0 - - - - - - - - - - - - - - - - - - - - dac_r a 45 112 l2 jtag_tms - - - - - - - - - - - - - - - - - - - - - - - - - - c_r a 46 111 l2 jtag_tck - - - - - - - - - - - - - - - - - - - - - - - - - - avss - 47 110 l2 jtag_tdi - - - - - - - - - - - - - - - - - - - - - - - - - - avcc3_dac - 48 109 m jtag_tdo - - - - - - - - - - - - - - - - - - - - - - - - - - dac_l a 49 108 l jtag_ntrst - - - - - - - - - - - - - - - - - - - - - - - - - - c_l a 50 107 k x0 - - - - - - - - - - - - - - - - - - - - - - - - - - avss - 51 106 k x1 - - - - - - - - - - - - - - - - - - - - - - - - - - vss - 52 105 - vss - - - - - - - - - - - - - 53 54 55 56 57 58 59 60 61 64 65 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 b b b b b b b b b b b c c c h h i r r vcc3 p0_21 p0_22 p0_23 p0_24 p0_25 vss p0_26 vss vcc3 p0_27 p0_28 p0_29 p0_30 p0_31 vss vcc3 p1_00 p1_01 p1_02 vcc12 vcc12 vss vcc5 p4_08 p4_09 p4_10 p4_11 p3_08 p3_09 p3_10 p3_11 p1_03 p1_04 p3_12 p3_13 p1_05 p1_06 p3_14 p3_15 p1_07 p1_08 p1_09 p4_12 p4_13 p1_10 p4_14 p4_15 nmix x0a x1a vcc5 m_sdata0_0 m_sdata0_2 m_sdata0_1 m_ssel0 m_sdata0_3 m_sclk0 m_sdata1_0 m_sdata1_2 m_sdata1_1 m_ssel1 m_sdata1_3 mlbclk mlbsig mlbdat an4 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 an15 an16 an17 an18 an21 p1_11 p1_12 m_dq3 m_dq2 m_dq1 m_dq0 m_cs#_1 m_ck m_rwds m_dq4 m_dq5 m_dq6 m_dq7 m_cs#_2 col_0 crs_0 eint13_3 eint14_3 eint15_3 eint16_3 eint18_1 eint6_1 eint17_3 eint8_1 eint4_0 eint5_0 eint21_1 eint18_3 eint6_0 eint7_0 eint12_1 eint19_3 eint8_0 adtrg1_1 eint10_0 eint20_3 eint21_3 eint11_0 eint22_3 eint23_3 eint12_0 eint13_0 txen_0 txd0_0 txd1_0 txd2_0 txd3_0 txer_0 rxd0_0 rxd1_0 rxd2_0 rxd3_0 mdio_0 mdc_0 eint11_3 eint12_3 sga0_1 sgo0_1 sga1_1 sgo1_1 bn0(bl0) bp0(bh0) sga2_1 sgo2_1 an0(al0) ap0(ah0) sga3_1 sgo3_1 bn1(bl1) eint9_0 an1(al1) ap1(ah1) ppg4_tout0_0 ppg4_tout2_0 eint2_0 eint1_3 eint2_3 eint3_3 eint4_3 eint5_3 eint6_3 eint3_0 eint7_3 eint8_3 eint9_3 eint10_3 scs32_0 scs33_0 ppg7_tout2_1 ppg0_tout0_0 ppg0_tout2_0 ppg8_tout0_1 ppg8_tout2_1 sga0_0 sgo0_0 ppg9_tout0_1 ppg9_tout2_1 sga1_0 bp1(bh1) sga2_0 sgo2_0 ocu8_otd0_0 ocu8_otd1_0 sin2_0 sck2_0 sot2_0 scs20_0 scs21_0 scs22_0 scs23_0 sin3_0 sck3_0 sot3_0 scs30_0 scs31_0 ppg6_tout0_1 ppg6_tout2_1 ppg7_tout0_1 ocu1_otd1_1 ocu0_otd0_0 ocu0_otd1_0 ocu2_otd0_1 ocu2_otd1_1 ppg1_tout0_0 ppg1_tout2_0 ocu8_otd0_1 ocu8_otd1_1 ppg2_tout0_0 sgo1_0 ppg3_tout0_0 ppg3_tout2_0 icu9_in0_0 icu9_in1_0 sin9_2 sot9_2 sck9_2 scs90_2 scs91_2 sin8_2 sck8_2 sot8_2 scs80_2 ocu0_otd0_1 ocu0_otd1_1 ocu1_otd0_1 icu1_in1_1 icu0_in0_0 icu0_in1_0 icu2_in0_1 icu2_in1_1 icu1_in0_0 icu1_in1_0 icu8_in0_1 icu8_in1_1 ocu1_otd0_0 ppg2_tout2_0 ocu2_otd0_0 ocu2_otd1_0 tin17_0 tot17_0 icu0_in0_1 icu0_in1_1 icu1_in0_1 tot1_1 ain8 bin8 tin16_1 tot16_1 zin8 ain9 tin17_1 tot17_1 icu2_in0_0 ocu1_otd1_0 icu8_in0_0 icu8_in1_0 rx2_0 tx2_0 tin0_1 tot0_1 tin1_1 rx1_1 tin0_0 tot0_0 tx1_1 sck10_1 tin1_0 tot1_0 rx2_1 tx2_1 bin9 icu2_in1_0 sck16_0 sot16_0 scs160_0 scs161_0 sin8_1 rx0_1 tx0_1 scs80_1 frt0/1/2/3_text frt4/8/9/10_text sin10_1 trace3_1 rx0_0 tx0_0 sot10_1 scs100_1 tin16_0 zin9 scl16 sda16 indicator0_0 sck8_1 sot8_1 trace1_1 sin0_0 sck0_0 trace2_1 sot0_0 scs00_0 trace_ctl_1 trace_clk_1 rx1_0 tot16_0 trace_ctl_0 trace_clk_0 trace0_1 scl0 sda0 trace1_0 trace2_0 tx1_0 trace0_0 sin16_0 trace3_0 top view teqfp-208
document number: 002- 10635 rev.** page 17 of 247 s6j33 10/20/30/40 series preliminar 2 teqf - 6 in ssinment s633 figure 4 - 2 : teqfp -176 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - lcdd4 lcdd3 lcdd0 scs43_0 scs42_0 lcdd2 lcdd1 sda4 scl4 scs32_1 scs31_1 scs23_1 scs22_1 scs21_1 scs20_1 sot2_1 scl12 sda11 scl11 sda10 scl10 sda9 scs41_0 scs40_0 sot4_0 sck4_0 sin4_0 scs33_1 eint20_5 eint19_5 scs30_1 sot3_1 sck3_1 sin3_1 ppg14_tout0_1 ppg13_tout2_1 ppg13_tout0_1 ppg12_tout2_1 ppg12_tout0_1 sda12 sck12_0 sin12_0 scs111_0 scs110_0 sot11_0 sck11_0 sin11_0 scs100_0 sot10_0 sck10_0 sin10_0 scs91_0 scs90_0 sot9_0 eint3_6 eint2_6 eint1_6 eint0_6 eint23_5 eint22_5 eint0_0 eint21_5 adtrg1_2 adtrg0_1 ppg12/13/14/15_tin1_1 ppg15_tout2_1 ppg15_tout0_1 ppg14_tout2_1 eint15_5 eint14_5 eint13_5 eint12_5 eint11_5 scs120_0 sot12_0 ppg12/13/14/15_tin1_0 ppg15_tout2_0 ppg15_tout0_0 ppg14_tout2_0 ppg14_tout0_0 ppg13_tout2_0 ppg13_tout0_0 ppg12_tout2_0 ppg12_tout0_0 ppg6/7/8/9/10/11_tin1_0 ppg11_tout2_0 ppg11_tout0_0 ppg10_tout2_0 ppg10_tout0_0 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 eint18_5 eint17_5 eint16_5 eint3_1 seg4 seg1 seg0 eint9_5 eint7_5 eint6_5 eint23_0 eint4_5 eint3_5 eint2_5 eint0_5 eint22_0 eint22_4 eint21_4 eint20_4 eint21_0 eint18_4 eint17_4 eint15_4 mad0 mdata7 mdata6 mdata5 mdata4 mdata3 mdata2 mdata1 mdata0 mcsx1 seg8 seg7 seg5 mcsx0 mdata11 mdata10 mdata9 mdata8 pwm2m5 pwm2p5 pwm1m5 pwm1p5 pwm2m4 pwm2p4 pwm1m4 pwm1p4 pwm2m3 pwm2p3 pwm1m3 pwm1p3 pwm2m2 pwm2p2 pwm1m2 pwm1p2 dsp0_r6_0 dsp0_r5_0 dsp0_r4_0 dsp0_r3_0 dsp0_r2_0 dsp0_r1_0 dsp0_r0_0 dsp0_clk_0 dsp0_vsync_0 dsp0_hsync_0 mdata15 mdata14 mdata13 mdata12 dsp0_en_0 i2s0_sck_1 i2s0_ws_1 i2s0_sd_1 i2s0_eclk_1 an63 an62 an61 an60 an59 an58 an57 an56 an55 an54 an53 an52 an51 an50 an49 an47 vss p2_19 p2_18 p2_17 p2_16 p2_15 p2_14 p2_13 p2_12 p2_11 p2_10 p3_31 p3_30 p3_29 p3_28 vcc53 vss vcc12 p2_09 p3_27 p3_26 p3_25 p3_24 dvcc dvss p2_08 p2_07 p2_06 p2_05 p2_04 p2_03 p2_02 p2_01 dvcc dvss p2_00 p1_31 p1_30 p1_29 p1_28 p1_27 p1_26 p1_25 dvcc p p p p p p p p p p p p p p p p 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 vcc53 - 1 132 - dvss - - - - - - - - - - - - - - - - - - - - - lcdd5 eint0_1 seg19 mad 1 dsp0_r7_0 p0_00 s 2 131 p p1_24 an46 pw m2m1 eint14_4 ppg9_tout2_0 sck9_0 scl9 - - - - - - - - - - - - lcdd6 arh0_aic1_tcki arh0_aic1_dnclk sin1_0 eint1_0 seg20 mad 2 dsp0_g0_0 p0_01 s 3 130 p p1_23 an45 pwm2p1 eint20_0 ppg9_tout0_0 sin9_0 - - - - - - - - - - - - lcdd7 arh0_aic1_dndata1 arh0_aic1_tda1 scl1 sck1_0 eint4_1 seg21 mad 3 dsp0_g1_0 p0_02 s 4 129 p p1_22 an44 pw m1m1 eint13_4 ppg8_tout2_0 tx6_0 scs80_0 - - - - - - - - - - - - lcdd8 arh0_aic1_dbg_out_1 sda1 sot1_0 eint5_1 seg22 mad 4 dsp0_g2_0 p0_03 s 5 128 p p1_21 an43 pwm1p1 eint19_0 ppg8_tout0_0 rx6_0 sot8_0 sda8 - - - - - - - - - - - lcdd9 arh0_aic1_dbg_out_0 sin0_1 scs10_0 eint11_1 seg23 mad 5 dsp0_g3_0 p0_04 s 6 127 p p1_20 an42 pw m2m0 eint12_4 ppg7_tout2_0 sck8_0 scl8 - - - - - - - - - - - lcdd10 arh0_aic1_dndata0 arh0_aic1_tda0 sot0_1 scs11_0 eint13_1 seg24 mad 6 dsp0_g4_0 p0_05 s 7 126 p p1_19 an41 pwm2p0 eint18_0 ppg7_tout0_0 sin8_0 - - - - - - - - - - lcdd11 arh0_aic1_upclk arh0_aic1_rck sck0_1 scs12_0 ppg0_tout0_1 eint15_1 seg25 mad 7 dsp0_g5_0 i2s1_eclk_0 p0_06 s 8 125 p p1_18 an40 pw m1m0 eint11_4 ppg6_tout2_0 tx5_0 scs171_0 - - - - - - - - - lcdd12 arh0_aic1_updata1 arh0_aic1_rda1 scs00_1 scs13_0 ppg0_tout2_1 eint23_1 seg26 mad 8 dsp0_g6_0 i2s1_sd_0 p0_07 s 9 124 p p1_17 an39 pwm1p0 eint17_0 ppg6_tout0_0 rx5_0 scs170_0 - - - - - - - - - - - lcdd13 arh0_aic1_updata0 arh0_aic1_rda0 ppg1_tout0_1 eint0_2 seg27 mad 9 dsp0_g7_0 i2s1_ws_0 p0_08 s 10 123 - dvcc - - - - - - - - - - - - - - - - lcdd14 arh0_aic0_tcki arh0_aic0_dnclk sin17_1 ppg1_tout2_1 eint1_2 seg28 mad 10 dsp0_b0_0 i2s1_sck_0 p0_09 s 11 122 - dvss - - - - - - - - - - - - - - - - lcdd15 arh0_aic0_dndata1 arh0_aic0_tda1 scs171_1 ppg2_tout0_1 eint5_2 seg29 mad 11 dsp0_b1_0 i2s0_eclk_0 p0_10 s 12 121 - avss - - - - - - - - - - - - - - - - - - lcdd16 arh0_aic0_dbg_out_1 ppg2_tout2_1 eint6_2 seg30 mad 12 dsp0_b2_0 i2s0_sd_0 p0_11 s 13 120 - avrl5 - - - - - - - - - - - - - - - - - - lcdd17 arh0_aic0_dbg_out_0 ppg3_tout0_1 eint7_2 seg31 mad 13 dsp0_b3_0 i2s0_ws_0 p0_12 s 14 119 - avrh5 - - - - - - - - - - - - - - - - - - cs# arh0_aic0_dbg_select ppg3_tout2_1 eint8_2 c o m0 mad 14 dsp0_b4_0 i2s0_sck_0 p0_13 s 15 118 - avcc5 - - - - - - - - - - - - - - - - - - - - - - - - - - vcc53 - 16 117 h p1_16 adtrg0_0 - eint9_4 sgo4_0 ppg0/1/2/3/4/5_tin1_0 ocu10_otd1_0 tot49_0 sot17_0 sda17 wot sysc0_clk_0 - - - - - - - - - - - - - - - vss - 17 116 - vcc5 - - - - - - - - - - - - - - - - - - - - - - - - - - vcc12 - 18 115 - vss - - - - - - - - - - - - - - - - - - - - - sin1_1 ppg4_tout0_1 eint1_1 mad 15 txd1_1 p3_00 t 19 114 - vcc12 - - - - - - - - - - - - - - - - - - - - - sck1_1 ppg4_tout2_1 eint9_2 mad 16 txd2_1 p3_01 t 20 113 - vcc12 - - - - - - - - - - - - - - - - - - - - - sot1_1 ppg5_tout0_1 eint10_2 mad 17 txd3_1 p3_02 t 21 112 h p1_15 an32 eint16_0 sga4_0 ppg5_tout2_0 ocu10_otd0_0 icu10_in1_0 tin49_0 sck17_0 sck12_1 scl17 indicator0_1 - - - - - - - - - - scs10_1 ppg5_tout2_1 eint11_2 mad 18 txer_1 p3_03 t 22 111 g p1_14 an31 eint15_0 sgo3_0 ppg5_tout0_0 ocu9_otd1_0 icu10_in0_0 tot48_0 tx3_0 sin17_0 sysc0_clk_1 - - - - - - - - - - - scs11_1 ppg0/1/2/3/4/5_tin1_1 eint12_2 mad 19 rxd0_1 p3_04 t 23 110 g p3_23 an30 eint4_4 tx6_1 scs120_1 - - - - - - - - - - - - - - - - - scs12_1 sin4_1 eint15_2 mad 20 rxd3_1 p3_05 t 24 109 g p3_22 an29 eint19_1 rx6_1 scs91_1 - - - - - - - - - - - - - - - - - scs13_1 sot4_1 eint16_2 mad 21 md io _1 p3_06 t 25 108 g p3_21 an28 eint3_4 tot49_1 scs90_1 - - - - - - - - - - - - - - - wr# arh0_aic1_dbg_select sck4_1 eint17_2 c o m1 mo ex dsp0_b5_0 p0_14 s 26 107 e p3_20 eint2_4 ppg6/7/8/9/10/11_tin1_1 tin49_1 tx5_1 sot9_1 - - - - - - - - - - - - - - - rd# scs40_1 eint18_2 c o m2 mw ex dsp0_b6_0 p0_15 s 27 106 e p3_19 eint17_1 ppg11_tout2_1 ocu10_otd1_1 icu10_in1_1 rx5_1 sck9_1 - - - - - - - - - - - - - arh0_aic0_dndata0 arh0_aic0_tda0 scs41_1 eint19_2 c o m3 mc lk dsp0_b7_1 p0_16 s 28 105 e p3_18 eint20_1 ppg11_tout0_1 ocu10_otd0_1 icu10_in0_1 sin9_1 - - - - - - - - - - - - - - - - - - scs42_1 eint20_2 md q m1 p3_07 t 29 104 - vss - - - - - - - - - - - - - - - - - - - - scs43_1 eint21_2 v0 md q m0 dsp0_b7_0 rxclk_0 p0_17 v 30 103 - c - - - - - - - - - - - - - - - - - - rs arh0_aic0_upclk arh0_aic0_rck eint22_2 v1 mc sx2 mdc_1 rxer_0 p0_18 v 31 102 o mo d e - - - - - - - - - - - - - - - - - - res# arh0_aic0_updata1 arh0_aic0_rda1 eint23_2 v2 mc sx3 col_1 rxdv_0 p0_19 v 32 101 d psc_1 - - - - - - - - - - - - - - - - - - te arh0_aic0_updata0 arh0_aic0_rda0 eint0_3 v3 mrdy crs_1 txclk_0 p0_20 u 33 100 n rstx - - - - - - - - - - - - - - - - - - - - - - - - - - vcc53 - 34 99 g p3_17 an26 eint0_4 sgo4_1 ppg10_tout2_1 ocu9_otd1_1 icu9_in1_1 tot48_1 tx3_1 - - - - - - - - - - - - - - - - - - vss - 35 98 g p3_16 an25 eint14_1 sga4_1 ppg10_tout0_1 ocu9_otd0_1 icu9_in0_1 tin48_1 rx3_1 - - - - - - - - - - - - - - - - - - avss - 36 97 g p1_13 an24 eint14_0 sga3_0 ocu9_otd0_0 tin48_0 rx3_0 - - - - - - - - - - - - - - - - - - - - dac_r a 37 96 l2 jtag_tms - - - - - - - - - - - - - - - - - - - - - - - - - - c_r a 38 95 l2 jtag_tck - - - - - - - - - - - - - - - - - - - - - - - - - - avss - 39 94 l2 jtag_tdi - - - - - - - - - - - - - - - - - - - - - - - - - - avcc3_dac - 40 93 m jtag_tdo - - - - - - - - - - - - - - - - - - - - - - - - - - dac_l a 41 92 l jtag_ntrst - - - - - - - - - - - - - - - - - - - - - - - - - - c_l a 42 91 k x0 - - - - - - - - - - - - - - - - - - - - - - - - - - avss - 43 90 k x1 - - - - - - - - - - - - - - - - - - - - - - - - - - vss - 44 89 - vss - - - - - - - - - - - - - 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 64 65 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 b b b b b b b b b b b c c c h h i r r vcc3 p0_21 p0_22 p0_23 p0_24 p0_25 vss p0_26 vss vcc3 p0_27 p0_28 p0_29 p0_30 p0_31 vss vcc3 p1_00 p1_01 p1_02 vcc12 vcc12 vss vcc5 p3_08 p3_09 p3_10 p3_11 p1_03 p1_04 p3_12 p3_13 p1_05 p1_06 p3_14 p3_15 p1_07 p1_08 p1_09 p1_10 nmix x0a x1a vcc5 m_sdata0_0 m_sdata0_2 m_sdata0_1 m_ssel0 m_sdata0_3 m_sclk0 m_sdata1_0 m_sdata1_2 m_sdata1_1 m_ssel1 m_sdata1_3 mlbclk mlbsig mlbdat an4 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 an15 an16 an17 an18 an21 p1_11 p1_12 m_dq3 m_dq2 m_dq1 m_dq0 m_cs#_1 m_ck m_rwds m_dq4 m_dq5 m_dq6 m_dq7 m_cs#_2 col_0 crs_0 eint18_1 eint6_1 eint17_3 eint8_1 eint4_0 eint5_0 eint21_1 eint18_3 eint6_0 eint7_0 eint12_1 eint19_3 eint8_0 adtrg1_1 eint10_0 eint11_0 eint12_0 eint13_0 txen_0 txd0_0 txd1_0 txd2_0 txd3_0 txer_0 rxd0_0 rxd1_0 rxd2_0 rxd3_0 mdio_0 mdc_0 eint11_3 eint12_3 sga0_1 sgo0_1 sga1_1 sgo1_1 bn0(bl0) bp0(bh0) sga2_1 sgo2_1 an0(al0) ap0(ah0) sga3_1 sgo3_1 bn1(bl1) eint9_0 an1(al1) ap1(ah1) ppg4_tout0_0 ppg4_tout2_0 eint2_0 eint1_3 eint2_3 eint3_3 eint4_3 eint5_3 eint6_3 eint3_0 eint7_3 eint8_3 eint9_3 eint10_3 scs32_0 scs33_0 ppg7_tout2_1 ppg0_tout0_0 ppg0_tout2_0 ppg8_tout0_1 ppg8_tout2_1 sga0_0 sgo0_0 ppg9_tout0_1 ppg9_tout2_1 sga1_0 bp1(bh1) sga2_0 sgo2_0 ocu8_otd0_0 ocu8_otd1_0 sin2_0 sck2_0 sot2_0 scs20_0 scs21_0 scs22_0 scs23_0 sin3_0 sck3_0 sot3_0 scs30_0 scs31_0 ppg6_tout0_1 ppg6_tout2_1 ppg7_tout0_1 ocu1_otd1_1 ocu0_otd0_0 ocu0_otd1_0 ocu2_otd0_1 ocu2_otd1_1 ppg1_tout0_0 ppg1_tout2_0 ocu8_otd0_1 ocu8_otd1_1 ppg2_tout0_0 sgo1_0 ppg3_tout0_0 ppg3_tout2_0 icu9_in0_0 icu9_in1_0 sin9_2 sot9_2 sck9_2 scs90_2 scs91_2 sin8_2 sck8_2 sot8_2 scs80_2 ocu0_otd0_1 ocu0_otd1_1 ocu1_otd0_1 icu1_in1_1 icu0_in0_0 icu0_in1_0 icu2_in0_1 icu2_in1_1 icu1_in0_0 icu1_in1_0 icu8_in0_1 icu8_in1_1 ocu1_otd0_0 ppg2_tout2_0 ocu2_otd0_0 ocu2_otd1_0 tin17_0 tot17_0 icu0_in0_1 icu0_in1_1 icu1_in0_1 tot1_1 ain8 bin8 tin16_1 tot16_1 zin8 ain9 tin17_1 tot17_1 icu2_in0_0 ocu1_otd1_0 icu8_in0_0 icu8_in1_0 tin0_1 tot0_1 tin1_1 tin0_0 tot0_0 sck10_ tin1_0 tot1_0 bin9 icu2_in sck16_ sot16_ scs160 scs161 sin8_1 rx0_1 tx0_1 scs80_1 frt0/1/2/3_tex frt4/8/9/10_te sin10_1 trace3_1 rx0_0 tx0_0 sot10_1 scs100_1 tin16_0 zin9 scl16 sda16 indicator0_0 sck8_1 sot8_1 trace1_1 sin0_0 sck0_0 trace2_1 sot0_0 scs00_0 trace_ctl_ trace_clk_ tot16_0 trace_ctl_ trace_clk_ trace0_1 scl0 sda0 trace1_0 trace2_0 trace0_0 sin16_0 trace3_0 top view teqfp-176
document number: 002- 10635 rev.** page 18 of 247 s6j33 10/20/30/40 series preliminar 4.1.3 teqfp - 144 pin assignment ( S6J3310 ) figure 4 - 3 : teqfp -144 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - lcdd4 lcdd3 lcdd0 scs43_0 scs42_0 lcdd2 lcdd1 sda4 scl4 scs32_1 scs31_1 scs23_1 scl12 sda11 scl11 sda10 scl10 sda9 scs41_0 scs40_0 sot4_0 sck4_0 sin4_0 scs33_1 eint20_5 eint19_5 ppg14_tout0_1 sda12 sck12_0 sin12_0 scs111_0 scs110_0 sot11_0 sck11_0 sin11_0 scs100_0 sot10_0 sck10_0 sin10_0 scs91_0 scs90_0 sot9_0 eint3_6 eint2_6 eint1_6 eint0_6 eint23_5 eint22_5 eint0_0 eint21_5 adtrg1_2 adtrg0_1 eint15_5 scs120_0 sot12_0 ppg12/13/14/15_tin1_0 ppg15_tout2_0 ppg15_tout0_0 ppg14_tout2_0 ppg14_tout0_0 ppg13_tout2_0 ppg13_tout0_0 ppg12_tout2_0 ppg12_tout0_0 ppg6/7/8/9/10/11_tin1_0 ppg11_tout2_0 ppg11_tout0_0 ppg10_tout2_0 ppg10_tout0_0 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg4 eint9_5 eint7_5 eint6_5 eint23_0 eint4_5 eint3_5 eint2_5 eint0_5 eint22_0 eint22_4 eint21_4 eint20_4 eint21_0 eint18_4 eint17_4 eint15_4 mad0 mdata7 mdata6 mdata5 mdata4 mdata3 mdata2 mdata1 mdata0 mcsx1 mcsx0 pwm2m5 pwm2p5 pwm1m5 pwm1p5 pwm2m4 pwm2p4 pwm1m4 pwm1p4 pwm2m3 pwm2p3 pwm1m3 pwm1p3 pwm2m2 pwm2p2 pwm1m2 pwm1p2 dsp0_r6_0 dsp0_r5_0 dsp0_r4_0 dsp0_r3_0 dsp0_r2_0 dsp0_r1_0 dsp0_r0_0 dsp0_clk_0 dsp0_vsync_0 dsp0_hsync_0 dsp0_en_0 an63 an62 an61 an60 an59 an58 an57 an56 an55 an54 an53 an52 an51 an50 an49 an47 vss p2_19 p2_18 p2_17 p2_16 p2_15 p2_14 p2_13 p2_12 p2_11 p2_10 vcc53 vss vcc12 p2_09 dvcc dvss p2_08 p2_07 p2_06 p2_05 p2_04 p2_03 p2_02 p2_01 dvcc dvss p2_00 p1_31 p1_30 p1_29 p1_28 p1_27 p1_26 p1_25 dvcc p p p p p p p p p p p p p p p p 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 vcc53 - 1 108 - dvss - - - - - - - - - - - - - - - - - - - - - lcdd5 eint0_1 seg19 mad 1 dsp0_r7_0 p0_00 s 2 107 p p1_24 an46 pw m2m1 eint14_4 ppg9_tout2_0 sck9_0 scl9 - - - - - - - - - - - - lcdd6 arh0_aic1_tcki arh0_aic1_dnclk sin1_0 eint1_0 seg20 mad 2 dsp0_g0_0 p0_01 s 3 106 p p1_23 an45 pwm2p1 eint20_0 ppg9_tout0_0 sin9_0 - - - - - - - - - - - - lcdd7 arh0_aic1_dndata1 arh0_aic1_tda1 scl1 sck1_0 eint4_1 seg21 mad 3 dsp0_g1_0 p0_02 s 4 105 p p1_22 an44 pw m1m1 eint13_4 ppg8_tout2_0 tx6_0 scs80_0 - - - - - - - - - - - - lcdd8 arh0_aic1_dbg_out_1 sda1 sot1_0 eint5_1 seg22 mad 4 dsp0_g2_0 p0_03 s 5 104 p p1_21 an43 pwm1p1 eint19_0 ppg8_tout0_0 rx6_0 sot8_0 sda8 - - - - - - - - - - - lcdd9 arh0_aic1_dbg_out_0 sin0_1 scs10_0 eint11_1 seg23 mad 5 dsp0_g3_0 p0_04 s 6 103 p p1_20 an42 pw m2m0 eint12_4 ppg7_tout2_0 sck8_0 scl8 - - - - - - - - - - - lcdd10 arh0_aic1_dndata0 arh0_aic1_tda0 sot0_1 scs11_0 eint13_1 seg24 mad 6 dsp0_g4_0 p0_05 s 7 102 p p1_19 an41 pwm2p0 eint18_0 ppg7_tout0_0 sin8_0 - - - - - - - - - - lcdd11 arh0_aic1_upclk arh0_aic1_rck sck0_1 scs12_0 ppg0_tout0_1 eint15_1 seg25 mad 7 dsp0_g5_0 i2s1_eclk_0 p0_06 s 8 101 p p1_18 an40 pw m1m0 eint11_4 ppg6_tout2_0 tx5_0 scs171_0 - - - - - - - - - lcdd12 arh0_aic1_updata1 arh0_aic1_rda1 scs00_1 scs13_0 ppg0_tout2_1 eint23_1 seg26 mad 8 dsp0_g6_0 i2s1_sd_0 p0_07 s 9 100 p p1_17 an39 pwm1p0 eint17_0 ppg6_tout0_0 rx5_0 scs170_0 - - - - - - - - - - - lcdd13 arh0_aic1_updata0 arh0_aic1_rda0 ppg1_tout0_1 eint0_2 seg27 mad 9 dsp0_g7_0 i2s1_ws_0 p0_08 s 10 99 - dvcc - - - - - - - - - - - - - - - - lcdd14 arh0_aic0_tcki arh0_aic0_dnclk sin17_1 ppg1_tout2_1 eint1_2 seg28 mad 10 dsp0_b0_0 i2s1_sck_0 p0_09 s 11 98 - dvss - - - - - - - - - - - - - - - - lcdd15 arh0_aic0_dndata1 arh0_aic0_tda1 scs171_1 ppg2_tout0_1 eint5_2 seg29 mad 11 dsp0_b1_0 i2s0_eclk_0 p0_10 s 12 97 - avss - - - - - - - - - - - - - - - - - - lcdd16 arh0_aic0_dbg_out_1 ppg2_tout2_1 eint6_2 seg30 mad 12 dsp0_b2_0 i2s0_sd_0 p0_11 s 13 96 - avrl5 - - - - - - - - - - - - - - - - - - lcdd17 arh0_aic0_dbg_out_0 ppg3_tout0_1 eint7_2 seg31 mad 13 dsp0_b3_0 i2s0_ws_0 p0_12 s 14 95 - avrh5 - - - - - - - - - - - - - - - - - - cs# arh0_aic0_dbg_select ppg3_tout2_1 eint8_2 c o m0 mad 14 dsp0_b4_0 i2s0_sck_0 p0_13 s 15 94 - avcc5 - - - - - - - - - - - - - - - - - - - - - - - - - - vcc53 - 16 93 h p1_16 adtrg0_0 - eint9_4 sgo4_0 ppg0/1/2/3/4/5_tin1_0 ocu10_otd1_0 tot49_0 sot17_0 sda17 wot sysc0_clk_0 - - - - - - - - - - - - - - - vss - 17 92 - vcc5 - - - - - - - - - - - - - - - - - - - - - - - - - - vcc12 - 18 91 - vss - - - - - - - - - - - - - - - - - - - wr# arh0_aic1_dbg_select sck4_1 eint17_2 c o m1 mo ex dsp0_b5_0 p0_14 s 19 90 - vcc12 - - - - - - - - - - - - - - - - - - - - rd# scs40_1 eint18_2 c o m2 mw ex dsp0_b6_0 p0_15 s 20 89 - vcc12 - - - - - - - - - - - - - - - - - - - arh0_aic0_dndata0 arh0_aic0_tda0 scs41_1 eint19_2 c o m3 mc lk dsp0_b7_1 p0_16 s 21 88 h p1_15 an32 eint16_0 sga4_0 ppg5_tout2_0 ocu10_otd0_0 icu10_in1_0 tin49_0 sck17_0 sck12_1 scl17 indicator0_1 - - - - - - - - - scs43_1 eint21_2 v0 md q m0 dsp0_b7_0 rxclk_0 p0_17 v 22 87 g p1_14 an31 eint15_0 sgo3_0 ppg5_tout0_0 ocu9_otd1_0 icu10_in0_0 tot48_0 tx3_0 sin17_0 sysc0_clk_1 - - - - - - - - rs arh0_aic0_upclk arh0_aic0_rck eint22_2 v1 mc sx2 mdc_1 rxer_0 p0_18 v 23 86 - vss - - - - - - - - - - - - - - - - - - res# arh0_aic0_updata1 arh0_aic0_rda1 eint23_2 v2 mc sx3 col_1 rxdv_0 p0_19 v 24 85 - c - - - - - - - - - - - - - - - - - - te arh0_aic0_updata0 arh0_aic0_rda0 eint0_3 v3 mrdy crs_1 txclk_0 p0_20 u 25 84 o mo d e - - - - - - - - - - - - - - - - - - - - - - - - - - vcc53 - 26 83 d psc_1 - - - - - - - - - - - - - - - - - - - - - - - - - - vss - 27 82 n rstx - - - - - - - - - - - - - - - - - - - - - - - - - - avss - 28 81 g p1_13 an24 eint14_0 sga3_0 ocu9_otd0_0 tin48_0 rx3_0 - - - - - - - - - - - - - - - - - - - - dac_r a 29 80 l2 jtag_tms - - - - - - - - - - - - - - - - - - - - - - - - - - c_r a 30 79 l2 jtag_tck - - - - - - - - - - - - - - - - - - - - - - - - - - avss - 31 78 l2 jtag_tdi - - - - - - - - - - - - - - - - - - - - - - - - - - avcc3_dac - 32 77 m jtag_tdo - - - - - - - - - - - - - - - - - - - - - - - - - - dac_l a 33 76 l jtag_ntrst - - - - - - - - - - - - - - - - - - - - - - - - - - c_l a 34 75 k x0 - - - - - - - - - - - - - - - - - - - - - - - - - - avss - 35 74 k x1 - - - - - - - - - - - - - - - - - - - - - - - - - - vss - 36 73 - vss - - - - - - - - - - - - - 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 64 65 67 68 69 70 71 72 b b b b b b b b b b b c c c h h i r r vcc3 p0_21 p0_22 p0_23 p0_24 p0_25 vss p0_26 vss vcc3 p0_27 p0_28 p0_29 p0_30 p0_31 vss vcc3 p1_00 p1_01 p1_02 vcc12 vcc12 vss vcc5 p1_03 p1_04 p1_05 p1_06 p1_07 p1_08 p1_09 p1_10 nmix x0a x1a vcc5 m_sdata0_0 m_sdata0_2 m_sdata0_1 m_ssel0 m_sdata0_3 m_sclk0 m_sdata1_0 m_sdata1_2 m_sdata1_1 m_ssel1 m_sdata1_3 mlbclk mlbsig mlbdat an8 an9 an12 an13 an16 an17 an18 an21 p1_11 p1_12 m_dq3 m_dq2 m_dq1 m_dq0 m_cs#_1 m_ck m_rwds m_dq4 m_dq5 m_dq6 m_dq7 m_cs#_2 col_0 crs_0 eint4_0 eint5_0 eint6_0 eint7_0 eint8_0 adtrg1_1 eint10_0 eint11_0 eint12_0 eint13_0 txen_0 txd0_0 txd1_0 txd2_0 txd3_0 txer_0 rxd0_0 rxd1_0 rxd2_0 rxd3_0 mdio_0 mdc_0 eint11_3 eint12_3 bn0(bl0) bp0(bh0) an0(al0) ap0(ah0) bn1(bl1) eint9_0 an1(al1) ap1(ah1) ppg4_tout0_0 ppg4_tout2_0 eint2_0 eint1_3 eint2_3 eint3_3 eint4_3 eint5_3 eint6_3 eint3_0 eint7_3 eint8_3 eint9_3 eint10_3 scs32_0 scs33_0 ppg0_tout0_0 ppg0_tout2_0 sga0_0 sgo0_0 sga1_0 bp1(bh1) sga2_0 sgo2_0 ocu8_otd0_0 ocu8_otd1_0 sin2_0 sck2_0 sot2_0 scs20_0 scs21_0 scs22_0 scs23_0 sin3_0 sck3_0 sot3_0 scs30_0 scs31_0 ocu0_otd0_0 ocu0_otd1_0 ppg1_tout0_0 ppg1_tout2_0 ppg2_tout0_0 sgo1_0 ppg3_tout0_0 ppg3_tout2_0 icu9_in0_0 icu9_in1_0 sin9_2 sot9_2 sck9_2 scs90_2 scs91_2 sin8_2 sck8_2 sot8_2 scs80_2 icu0_in0_0 icu0_in1_0 icu1_in0_0 icu1_in1_0 ocu1_otd0_0 ppg2_tout2_0 ocu2_otd0_0 ocu2_otd1_0 tin17_0 tot17_0 ain8 bin8 zin8 ain9 icu2_in0_0 ocu1_otd1_0 icu8_in0_0 icu8_in1_0 tin0_0 tot0_0 tin1_0 tot1_0 bin9 icu2_in1_0 sck16_0 sot16_0 scs160_0 scs161_0 frt0/1/2/3_text frt4/8/9/10_text rx0_0 tx0_0 tin16_0 zin9 scl16 sda16 indicator0_0 sin0_0 sck0_0 sot0_0 scs00_0 tot16_0 trace_ctl_0 trace_clk_0 scl0 sda0 trace1_0 trace2_0 trace0_0 sin16_0 trace3_0 top view teqfp-144
document number: 002- 10635 rev.** page 19 of 247 s6j33 10/20/30/40 series preliminar 4.2 package dimensions 4.2.1 teqfp208 figure 4 - 4 : teqfp208
document number: 002- 10635 rev.** page 20 of 247 s6j33 10/20/30/40 series preliminar 4.2.2 teqfp176 figure 4 - 5 : teqfp176
document number: 002- 10635 rev.** page 21 of 247 s6j33 10/20/30/40 series preliminar 4.2.3 teqfp144 figure 4 - 6 : teqfp144
document number: 002- 10635 rev.** page 22 of 247 s6j33 10/20/30/40 series preliminar figure 4 - 7 : teqfp144
document number: 002- 10635 rev.** page 23 of 247 s6j33 10/20/30/40 series preliminar 5. io circuit type 5.1 i/o circuit type this section explains i/o circuit types. type circuit remark a ? analog output(3v) ? audio dac output b ? general - purpose i/o port ? output 2ma, 5ma, 6ma or 15ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? ttl input c ? general - purpose i/o port ? output 2ma, 5ma, 6ma or 15ma selectable ? 50 k with pull - up resistor control ? 50 k with pull - down resistor control ? cmos hysteresis input ? medialb level hysteresis input d ? external 1.2v regulator control ? output 2ma e ? general - purpose i/o port ? output 1ma, 2ma or 5ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input analog output pull - up control digital output digital output pull - down control pss control ttl input pss control cmos - hys input pull - up control digital output digital output pull - down control pss control medialb - hys input pss control cmos - hys input digital output digital output pull - up control digital output digital output pull - down control pss control automotive input pss control cmos - hys input
document number: 002- 10635 rev.** page 24 of 247 s6j33 10/20/30/40 series preliminar type circuit remark g ? general - purpose i/o port with analog input ? output 1ma, 2ma or 5ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input h ? general - purpose i/o port with analog input ? output 1ma, 2ma, 3ma(i 2 c) or 5ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input ? ttl input i ? 50k with pull - up ? cmos hysteresis input k ? main oscillation i/o l ? jtag_ntrst ? 50k with pull - down ? ttl input pull - up control digital output digital output pull - down control pss control automotive input pss control cmos - hys input analog input pull - up control digital output digital output pull - down control pss control automotive input pss control cmos - hys input analog input ttl input pss control cmos - hys input pss control osc input x0 x1 ttl input
document number: 002- 10635 rev.** page 25 of 247 s6j33 10/20/30/40 series preliminar type circuit remark l2 ? jtag_tdi/tms/tck ? 50k with pull - up ? ttl input m ? jtag_tdo ? output 5ma n ? rstx input ? 50k with pull - up ? cmos hysteresis input o ? cmos hysteresis input p ? general - purpose i/o port with analog input ? output 1ma, 2ma, 5ma or 30ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input q ? general - purpose i/o port ? output 1ma, 2ma, 5ma or 30ma selectable ? 50k with pull - up resistor cont rol ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input ttl input digital output digital output pull - up control digital output digital output pull - down control pss control automotive input pss control cmos - hys input analog input pull - up control digital output digital output pull - down control pss control automotive input pss control cmos - hys input reset input cmos - hys input
document number: 002- 10635 rev.** page 26 of 247 s6j33 10/20/30/40 series preliminar type circuit remark r ? sub oscillation i/o shared general - purpose i/o port ? output 1ma, 2ma or 5ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input s ? general - purpose i/o port with lcdc com/seg output ? output 1ma, 2ma or 5ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input ? ttl input pss/osc control osc input pull - up control digital output digital output pull - down control pss/osc control automotive input pss/osc control cmos - hys input pull - up control digital output digital output pull - down control pss/osc control automotive input pss/osc control cmos - hys input pull - up control digital output digital output pull - down control pss control automotive input pss control cmos - hys input lcdc com/seg output ttl input pss control
document number: 002- 10635 rev.** page 27 of 247 s6j33 10/20/30/40 series preliminar type circuit remark s2 ? general - purpose i/o port with lcdc com/seg output ? output 1ma, 2ma, 5ma or 15ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input ? ttl input t ? genera l - purpose i/o port ? output 1ma, 2ma or 5ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input ? ttl input u ? general - purpose input port with lcdc reference voltage input ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? auto motive hysteresis input ? ttl input pull - up control digital output digital output pull - down control pss control automotive input pss control cmos - hys input lcdc com/seg output ttl input pss control pull - up control digital output digital output pull - down control pss control automotive input pss control cmos - hys input ttl input pss control p ull - up control pull - down control pss control; automotive input pss control ; cmos - hys input ttl input pss control lcdc reference voltage input
document number: 002- 10635 rev.** page 28 of 247 s6j33 10/20/30/40 series preliminar type circuit remark v ? general - purpose i/o port with lcdc reference voltage input ? output 1ma, 2ma or 5ma selectable ? 50k with pull - up resistor control ? 50k with pull - down resistor control ? cmos hysteresis input ? automotive hysteresis input ? ttl input 5.2 note alphabet which shows i/o circuit type is described with corresponding pin number in pin assignment figure. pull - up control digital output pull - down control pss control; automotive input pss control cmos - hys input ttl input pss control lcdc reference voltage input digital output
document number: 002- 10635 rev.** page 29 of 247 s6j33 10/20/30/40 series preliminar 6. port description 6.1 port description list the table shows the port function of description which is supported. the port function which is not describe d in the table is not supported for the product. S6J3310 port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 vcc12 1.2v external power supply pin 18, 57, 58, 89, 90, 131 18, 65, 66, 113, 114, 159 24, 73, 74, 132, 133, 191 vcc5 5v external power supply pin 60, 72, 92 68, 88, 116 76, 104, 135, vcc3 3v external power supply pin 37, 46, 53 45, 54, 61 53, 69 vcc53 3v/5v external power supply pin 1, 16, 26, 133 1, 16, 34, 161 1, 42, 193 vss gnd 17, 27, 36, 43, 45, 52, 59, 73, 86, 91, 132, 144 17, 35, 44, 51, 53, 60, 67, 89, 104, 115, 160, 176 43, 52, 59, 61, 68, 75, 105, 121, 134, 192, 208 avcc3_dac audio dac power supply pin 40 48 avcc5 a/d converter analog power supply pin 94 118 142 avrh5 a/d converter upper limit reference voltage pin 95 119 143 avrl5 a/d converter lower limit reference voltage pin 96 120 144 avss a/d converter gnd 28, 31, 35, 97 39, 43, 121 44, 47, 51, 145 dvcc smc large current port power supply pin 99 109 119 129 123 133 143 153 147 157 170 183 dvss smc large current port gnd 98 108 118 128 122 132 142 152 146 156 169 182 x1 main clock oscillator output pin 74 90 106 x0 main clock oscillator input pin 75 91 107 x1a sub clock oscillator output 71 87 103 x0a sub clock oscillator input 70 86 102 nmix non maskable interrupt input pin 69 85 101
document number: 002- 10635 rev.** page 30 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 rstx external reset input pin 82 100 117 psc_1 external power supply control pin 83 101 118 mode mode pin 84 102 119 c external capacity connection output pin 85 103 120 jtag_n trs t jtag test reset input pin 76 92 108 jtag_ tdo jtag test data output pin 77 93 109 jtag_ tdi jtag test data input pin 78 94 110 jtag_ tck jtag test clock input pin 79 95 111 jtag_ tms jtag test mode state input pin 80 96 112 trace0_0 trace data 0 output pin (0) 63 77 89 trace1_0 trace data 1 output pin (0) 64 78 90 trace2_0 trace data 2 output pin (0) 65 81 93 trace3_0 trace data 3 output pin (0) 66 82 94 trace_clk_0 trace clock (0) 68 84 98 trace_ctl_0 trace control (0) 67 83 95 trace0_1 trace data 0 output pin (1) - 71 83 trace1_1 trace data 1 output pin (1) - 72 84 trace2_1 trace data 2 output pin (1) - 75 87 trace3_1 trace data 3 output pin (1) - 76 88 trace_clk_1 trace clock (1) - 80 92 trace_ctl_1 trace control (1) - 79 91 adtrg0_ 0 a/d converter external trigger input pin (0) 93 117 139 adtrg1_0 a/d converter external trigger input pin (0) - - 140 adtrg0_1 a/d converter external trigger input pin (1) 134 166 198 adtrg1_1 a/d converter external trigger input pin (1) 66 82 94 adtrg1_2 a/d converter external trigger input pin (2) 135 167 199 an4 adc analog 4 input pin - 69 81 an5 adc analog 5 input pin - 70 82 an6 adc analog 6 input pin - 71 83 an7 adc analog 7 input pin - 72 84 an8 adc analog 8 input pin 61 73 85 an9 adc analog 9 input pin 62 74 86 an10 adc analog 10 input pin - 75 87 an11 adc analog 11 input pin - 76 88 an12 adc analog 12 input pin 63 77 89 an13 adc analog 13 input pin 64 78 90 an14 adc analog 14 input pin - 79 91 an15 adc analog 15 input pin - 80 92 an16 adc analog 16 input pin 65 81 93 an17 adc analog 17 input pin 66 82 94 an18 adc analog 18 input pin 67 83 95 an21 adc analog 21 input pin 68 84 98 an24 adc analog 24 input pin 81 97 113 an25 adc analog 25 input pin - 98 114 an26 adc analog 26 input pin - 99 115 an28 adc analog 28 input pin - 108 125 an29 adc analog 29 input pin - 109 126 an30 adc analog 30 input pin - 110 127 an31 adc analog 31 input pin 87 111 128
document number: 002- 10635 rev.** page 31 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 an32 adc analog 32 input pin 88 112 129 an39 adc analog 39 input pin 100 124 148 an40 adc analog 40 input pin 101 125 149 an41 adc analog 41 input pin 102 126 150 an42 adc analog 42 input pin 103 127 151 an43 adc analog 43 input pin 104 128 152 an44 adc analog 44 input pin 105 129 153 an45 adc analog 45 input pin 106 130 154 an46 adc analog 46 input pin 107 131 155 an47 adc analog 47 input pin 110 134 158 an49 adc analog 49 input pin 111 135 160 an50 adc analog 50 input pin 112 136 161 an51 adc analog 51 input pin 113 137 162 an52 adc analog 52 input pin 114 138 164 an53 adc analog 53 input pin 115 139 165 an54 adc analog 54 input pin 116 140 166 an55 adc analog 55 input pin 117 141 168 an56 adc analog 56 input pin 120 144 171 an57 adc analog 57 input pin 121 145 173 an58 adc analog 58 input pin 122 146 174 an59 adc analog 59 input pin 123 147 175 an60 adc analog 60 input pin 124 148 177 an61 adc analog 61 input pin 125 149 178 an62 adc analog 62 input pin 126 150 179 an63 adc analog 63 input pin 127 151 181 tx0_0 can transmission data 0 output pin (0) 64 78 90 tx1_0 can transmission data 1 output pin (0) - - 94 tx2_0 can transmission data 2 output pin (0) - - 103 tx3_0 can transmission data 3 output pin (0) 87 111 128 tx5_0 can transmission data 5 output pin (0) 101 125 149 tx6_0 can transmission data 6 output pin (0) 105 129 153 tx0_1 can transmission data 0 output pin (1) - 71 83 tx1_1 can transmission data 1 output pin (1) - - 87 tx2_1 can transmission data 2 output pin (1) - - 92 tx3_1 can transmission data 3 output pin (1) - 99 115 tx5_1 can transmission data 5 output pin (1) - 107 124 tx6_1 can transmission data 6 output pin (1) - 110 127 tx0_2 can transmission data 0 output pin (2) - - 7 tx3_2 can transmission data 3 output pin (2) - - 16 rx0_0 can reception data 0 input pin (0) 63 77 89 rx1_0 can reception data 1 input pin (0) - - 93 rx2_0 can reception data 2 input pin (0) - - 102 rx3_0 can reception data 3 input pin (0) 81 97 113 rx5_0 can reception data 5 input pin (0) 100 124 148 rx6_0 can reception data 6 input pin (0) 104 128 152 rx0_1 can reception data 0 input pin (1) - 70 82 rx1_1 can reception data 1 input pin (1) - - 84 rx2_1 can reception data 2 input pin (1) - - 91 rx3_1 can reception data 3 input pin (1) - 98 114
document number: 002- 10635 rev.** page 32 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 rx5_1 can reception data 5 input pin (1) - 106 123 rx6_1 can reception data 6 input pin (1) - 109 126 rx0_2 can reception data 0 input pin (2) - - 6 rx3_2 can reception data 3 input pin (2) - - 15 eint0_0 external interrupt input pin (0) 137 169 201 eint1_0 external interrupt input pin (0) 3 3 3 eint2_0 external interrupt input pin (0) 38 46 54 eint3_0 external interrupt input pin (0) 48 56 64 eint4_0 external interrupt input pin (0) 61 73 85 eint5_0 external interrupt input pin (0) 62 74 86 eint6_0 external interrupt input pin (0) 63 77 89 eint7_0 external interrupt input pin (0) 64 78 90 eint8_0 external interrupt input pin (0) 65 81 93 eint9_0 external interrupt input pin (0) 66 82 94 eint10_0 external interrupt input pin (0) 67 83 95 eint11_0 external interrupt input pin (0) 68 84 98 eint12_0 external interrupt input pin (0) 70 86 102 eint13_0 external interrupt input pin (0) 71 87 103 eint14_0 external interrupt input pin (0) 81 97 113 eint15_0 external interrupt input pin (0) 87 111 128 eint16_0 external interrupt input pin (0) 88 112 129 eint17_0 external interrupt input pin (0) 100 124 148 eint18_0 external interrupt input pin (0) 102 126 150 eint19_0 external interrupt input pin (0) 104 128 152 eint20_0 external interrupt input pin (0) 106 130 154 eint21_0 external interrupt input pin (0) 113 137 162 eint22_0 external interrupt input pin (0) 117 141 168 eint23_0 external interrupt input pin (0) 124 148 177 eint0_1 external interrupt input pin (1) 2 2 2 eint1_1 external interrupt input pin (1) - 19 25 eint2_1 external interrupt input pin (1) - - 184 eint3_1 external interrupt input pin (1) - 162 194 eint4_1 external interrupt input pin (1) 4 4 4 eint5_1 external interrupt input pin (1) 5 5 5 eint6_1 external interrupt input pin (1) - 70 82 eint7_1 external interrupt input pin (1) - - 6 eint8_1 external interrupt input pin (1) - 72 84 eint9_1 external interrupt input pin (1) - - 7 eint10_1 external interrupt input pin (1) - - 8 eint11_1 external interrupt input pin (1) 6 6 9 eint12_1 external interrupt input pin (1) - 79 91 eint13_1 external interrupt input pin (1) 7 7 10 eint14_1 external interrupt input pin (1) - 98 114 eint15_1 external interrupt input pin (1) 8 8 11 eint16_1 external interrupt input pin (1) - - 136 eint17_1 external interrupt input pin (1) - 106 123 eint18_1 external interrupt input pin (1) - 69 81 eint19_1 external interrupt input pin (1) - 109 126 eint20_1 external interrupt input pin (1) - 105 122
document number: 002- 10635 rev.** page 33 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 eint21_1 external interrupt input pin (1) - 75 87 eint22_1 external interrupt input pin (1) - - 140 eint23_1 external interrupt input pin (1) 9 9 12 eint0_2 external interrupt input pin (2) 10 10 13 eint1_2 external interrupt input pin (2) 11 11 14 eint2_2 external interrupt input pin (2) - - 15 eint3_2 external interrupt input pin (2) - - 16 eint4_2 external interrupt input pin (2) - - 17 eint5_2 external interrupt input pin (2) 12 12 18 eint6_2 external interrupt input pin (2) 13 13 19 eint7_2 external interrupt input pin (2) 14 14 20 eint8_2 external interrupt input pin (2) 15 15 21 eint9_2 external interrupt input pin (2) - 20 26 eint10_2 external interrupt input pin (2) - 21 27 eint11_2 external interrupt input pin (2) - 22 28 eint12_2 external interrupt input pin (2) - 23 29 eint13_2 external interrupt input pin (2) - - 30 eint14_2 external interrupt input pin (2) - - 31 eint15_2 external interrupt input pin (2) - 24 32 eint16_2 external interrupt input pin (2) - 25 33 eint17_2 external interrupt input pin (2) 19 26 34 eint18_2 external interrupt input pin (2) 20 27 35 eint19_2 external interrupt input pin (2) 21 28 36 eint20_2 external interrupt input pin (2) - 29 37 eint21_2 external interrupt input pin (2) 22 30 38 eint22_2 external interrupt input pin (2) 23 31 39 eint23_2 external interrupt input pin (2) 24 32 40 eint0_3 external interrupt input pin (3) 25 33 41 eint1_3 external interrupt input pin (3) 39 47 55 eint2_3 external interrupt input pin (3) 40 48 56 eint3_3 external interrupt input pin (3) 41 49 57 eint4_3 external interrupt input pin (3) 42 50 58 eint5_3 external interrupt input pin (3) 44 52 60 eint6_3 external interrupt input pin (3) 47 55 63 eint7_3 external interrupt input pin (3) 49 57 65 eint8_3 external interrupt input pin (3) 50 58 66 eint9_3 external interrupt input pin (3) 51 59 67 eint10_3 external interrupt input pin (3) 54 62 70 eint11_3 external interrupt input pin (3) 55 63 71 eint12_3 external interrupt input pin (3) 56 64 72 eint13_3 external interrupt input pin (3) - - 77 eint14_3 external interrupt input pin (3) - - 78 eint15_3 external interrupt input pin (3) - - 79 eint16_3 external interrupt input pin (3) - - 80 eint17_3 external interrupt input pin (3) - 71 83 eint18_3 external interrupt input pin (3) - 76 88 eint19_3 external interrupt input pin (3) - 80 92 eint20_3 external interrupt input pin (3) - - 96 eint21_3 external interrupt input pin (3) - - 97
document number: 002- 10635 rev.** page 34 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 eint22_3 external interrupt input pin (3) - - 99 eint23_3 external interrupt input pin (3) - - 100 eint0_4 external interrupt input pin (4) - 99 115 eint1_4 external interrupt input pin (4) - - 116 eint2_4 external interrupt input pin (4) - 107 124 eint3_4 external interrupt input pin (4) - 108 125 eint4_4 external interrupt input pin (4) - 110 127 eint5_4 external interrupt input pin (4) - - 130 eint6_4 external interrupt input pin (4) - - 131 eint7_4 external interrupt input pin (4) - - 137 eint8_4 external interrupt input pin (4) - - 138 eint9_4 external interrupt input pin (4) 93 117 139 eint10_4 external interrupt input pin (4) - - 141 eint11_4 external interrupt input pin (4) 101 125 149 eint12_4 external interrupt input pin (4) 103 127 151 eint13_4 external interrupt input pin (4) 105 129 153 eint14_4 external interrupt input pin (4) 107 131 155 eint15_4 external interrupt input pin (4) 110 134 158 eint16_4 external interrupt input pin (4) - - 159 eint17_4 external interrupt input pin (4) 111 135 160 eint18_4 external interrupt input pin (4) 112 136 161 eint19_4 external interrupt input pin (4) - - 163 eint20_4 external interrupt input pin (4) 114 138 164 eint21_4 external interrupt input pin (4) 115 139 165 eint22_4 external interrupt input pin (4) 116 140 166 eint23_4 external interrupt input pin (4) - - 167 eint0_5 external interrupt input pin (5) 120 144 171 eint1_5 external interrupt input pin (5) - - 172 eint2_5 external interrupt input pin (5) 121 145 173 eint3_5 external interrupt input pin (5) 122 146 174 eint4_5 external interrupt input pin (5) 123 147 175 eint5_5 external interrupt input pin (5) - - 176 eint6_5 external interrupt input pin (5) 125 149 178 eint7_5 external interrupt input pin (5) 126 150 179 eint8_5 external interrupt input pin (5) - - 180 eint9_5 external interrupt input pin (5) 127 151 181 eint10_5 external interrupt input pin (5) - - 185 eint11_5 external interrupt input pin (5) - 154 186 eint12_5 external interrupt input pin (5) - 155 187 eint13_5 external interrupt input pin (5) - 156 188 eint14_5 external interrupt input pin (5) - 157 189 eint15_5 external interrupt input pin (5) 130 158 190 eint16_5 external interrupt input pin (5) - 163 195 eint17_5 external interrupt input pin (5) - 164 196 eint18_5 external interrupt input pin (5) - 165 197 eint19_5 external interrupt input pin (5) 134 166 198 eint20_5 external interrupt input pin (5) 135 167 199 eint21_5 external interrupt input pin (5) 136 168 200 eint22_5 external interrupt input pin (5) 138 170 202
document number: 002- 10635 rev.** page 35 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 eint23_5 external interrupt input pin (5) 139 171 203 eint0_6 external interrupt input pin (6) 140 172 204 eint1_6 external interrupt input pin (6) 141 173 205 eint2_6 external interrupt input pin (6) 142 174 206 eint3_6 external interrupt input pin (6) 143 175 207 scs00_0 multi - function serial ch.0 chip select 0 i/o pin (0) 64 78 90 scs10_0 multi - function serial ch.1 chip select 0 i/o pin (0) 6 6 9 scs11_0 multi - function serial ch.1 chip select 1 output pin (0) 7 7 10 scs12_0 multi - function serial ch.1 chip select 2 output pin (0) 8 8 11 scs13_0 multi - function serial ch.1 chip select 3 output pin (0) 9 9 12 scs20_0 multi - function serial ch.2 chip select 0 i/o pin (0) 41 49 57 scs21_0 multi function serial ch.2 chip select 1 output pin (0) 42 50 58 scs22_0 multi - function serial ch.2 chip select 2 output pin (0) 44 52 60 scs23_0 multi function serial ch.2 chip select 3 output pin (0) 47 55 scs30_0 multi - function serial ch.3 chip select 0 i/o pin (0) 51 59 67 scs31_0 multi function serial ch.3 chip select 1 output pin (0) 54 70 scs32_0 multi - function serial ch.3 chip select 2 output pin (0) 55 71 scs33_0 multi function serial ch.3 chip select 3 output pin (0) 56 64 72 scs40_0 multi - function serial ch.4 chip select 0 i/o pin (0) 140 172 204 scs41_0 multi function serial ch.4 chip select 1 output pin (0) 141 173 205 scs42_0 multi - function serial ch.4 chip select 2 output pin (0) 142 174 206 scs43_0 multi function serial ch.4 chip select 3 output pin (0) 143 175 207 scs80_0 multi - function serial ch.8 chip select 0 i/o pin (0) 105 129 153 scs90_0 multi function serial ch.9 chip select 0 i/o pin (0) 111 135 160 scs91_0 multi - function serial ch.9 chip select 1 output pin (0) 112 136 161 scs100_0 multi function serial ch.10 chip select 0 i/o pin (0) 116 140 166 scs110_0 multi - function serial ch.11 chip select 0 i/o pin (0) 122 146 174 scs111_0 multi function serial ch.11 chip select 1 output pin (0) 123 147 175 scs120_0 multi - function serial ch.12 chip select 0 i/o pin (0) 127 151 181 scs160_0 multi function serial ch.16 chip select 0 i/o pin (0) 70 86 102 scs161_0 multi - function serial ch.16 chip select 1 output pin (0) 71 87 103 scs170_0 multi function serial ch.17 chip select 0 i/o pin (0) 100 124 148 scs171_0 multi - function serial ch.17 chip select 1 output pin (0) 101 125 149 scs00_1 multi function serial ch.0 chip select 0 i/o pin (1) 9 9 12 scs10_1 multi - function serial ch.1 chip select 0 i/o pin (1) - 22 28 scs11_1 multi function serial ch.1 chip select 1 output pin (1) 29 scs12_1 multi - function serial ch.1 chip select 2 output pin (1) - 24 scs13_1 multi function serial ch.1 chip select 3 output pin (1) 25 scs20_1 multi - function serial ch.2 chip select 0 i/o pin (1) - 155 187 scs21_1 multi function serial ch.2 chip select 1 output pin (1) 156 188 scs22_1 multi - function serial ch.2 chip select 2 output pin (1) - 157 189 scs23_1 multi function serial ch.2 chip select 3 output pin (1) 130 158 190 scs30_1 multi - function serial ch.3 chip select 0 i/o pin (1) - 165 197 scs31_1 multi function serial ch.3 chip select 1 output pin (1) 134 166 198 scs32_1 multi - function serial ch.3 chip select 2 output pin (1) 135 167 199 scs33_1 multi function serial ch.3 chip select 3 output pin (1) 136 168 200 scs40_1 multi function serial ch.4 chip select 0 i/o pin (1) 20 27 35 scs41_1 multi function serial ch.4 chip select 1 output pin (1) 21 28 scs42_1 multi function serial ch.4 chip select 2 output pin (1) 29 37
document number: 002- 10635 rev.** page 36 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 scs43_1 multi - function serial ch.4 chip select 3 output pin (1) 22 30 38 scs80_1 multi - function serial ch.8 chip select 0 i/o pin (1) - 72 84 scs90_1 multi - function serial ch.9 chip select 0 i/o pin (1) - 108 125 scs91_1 multi function serial ch.9 chip select 1 output pin (1) 109 126 scs100_1 multi - function serial ch.10 chip select 0 i/o pin (1) - 80 92 scs120_1 multi function serial ch.12 chip select 0 i/o pin (1) 110 127 scs160_1 multi - function serial ch.16 chip select 0 i/o pin (1) - - 141 scs161_1 multi function serial ch.16 chip select 1 output pin (1) 140 scs170_1 multi - function serial ch.17 chip select 0 i/o pin (1) - - 15 scs171_1 multi function serial ch.17 chip select 1 output pin (1) 12 12 18 scs80_2 multi - function serial ch.8 chip select 0 i/o pin (2) 50 58 scs90_2 multi function serial ch.9 chip select 0 i/o pin (2) 41 49 57 scs91_2 multi - function serial ch.9 chip select 1 output pin (2) 42 50 58 sck0_0 multi function serial ch.0 clock i/o pin (0) 74 86 sck1_0 multi function serial ch.1 clock i/o pin (0) 4 4 4 sck2_0 multi function serial ch.2 clock i/o pin (0) 39 47 55 sck3_0 multi function serial ch.3 clock i/o pin (0) 49 57 65 sck4_0 multi function serial ch.4 clock i/o pin (0) 138 170 202 sck8_0 multi function serial ch.8 clock i/o pin (0) 103 127 151 sck9_0 multi function serial ch.9 clock i/o pin (0) 107 131 155 sck10_0 multi function serial ch.10 clock i/o pin (0) 114 138 164 sck11_0 multi function serial ch.11 clock i/o pin (0) 120 144 171 sck12_0 multi function serial ch.12 clock i/o pin (0) 125 149 178 sck16_0 multi function serial ch.16 clock i/o pin (0) 67 83 95 sck17_0 multi function serial ch.17 clock i/o pin (0) 88 112 129 sck0_1 multi function serial ch.0 clock i/o pin (1) 8 8 11 sck1_1 multi function serial ch.1 clock i/o pin (1) 20 sck2_1 multi function serial ch.2 clock i/o pin (1) 185 sck3_1 multi function serial ch.3 clock i/o pin (1) 163 195 sck4_1 multi function serial ch.4 clock i/o pin (1) 19 34 sck8_1 multi function serial ch.8 clock i/o pin (1) 70 82 sck9_1 multi function serial ch.9 clock i/o pin (1) 106 123 sck10_1 multi function serial ch.10 clock i/o pin (1) 76 88 sck12_1 multi function serial ch.12 clock i/o pin (1) 88 112 129 sck16_1 multi function serial ch.16 clock i/o pin (1) 138 sck17_1 multi function serial ch.17 clock i/o pin (1) 16 sck8_2 multi function serial ch.8 clock i/o pin (2) 48 56 64 sck9_2 multi function serial ch.9 clock i/o pin (2) 40 48 56 sin0_0 multi function serial ch.0 serial data input pin (0) 61 73 85 sin1_0 multi function serial ch.1 serial data input pin (0) sin2_0 multi function serial ch.2 serial data input pin (0) 38 46 54 sin3_0 multi function serial ch.3 serial data input pin (0) 48 56 64 sin4_0 multi function serial ch.4 serial data input pin (0) 137 169 201 sin8_0 multi function serial ch.8 serial data input pin (0) 102 126 150 sin9_0 multi function serial ch.9 serial data input pin (0) 106 130 154 sin10_0 multi function serial ch.10 serial data input pin (0) 113 137 162 sin11_0 multi function serial ch.11 serial data input pin (0) 117 141 168 sin12_0 multi function serial ch.12 serial data input pin (0) 124 148 177 sin16_0 multi function serial ch.16 serial data input pin (0) 82 94
document number: 002- 10635 rev.** page 37 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 sin17_0 multi - function serial ch.17 serial data input pin (0) 87 111 128 sin0_1 multi - function serial ch.0 serial data input pin (1) 6 6 9 sin1_1 multi - function serial ch.1 serial data input pin (1) - 19 25 sin2_1 multi - function serial ch.2 serial data input pin (1) - - 184 sin3_1 multi - function serial ch.3 serial data input pin (1) - 162 194 sin4_1 multi - function serial ch.4 serial data input pin (1) - 24 32 sin8_1 multi - function serial ch.8 serial data input pin (1) - 69 81 sin9_1 multi - function serial ch.9 serial data input pin (1) - 105 122 sin10_1 multi - function serial ch.10 serial data input pin (1) - 75 87 sin12_1 multi - function serial ch.12 serial data input pin (1) - - 131 sin16_1 multi - function serial ch.16 serial data input pin (1) - - 136 sin17_1 multi - function serial ch.17 serial data input pin (1) 11 11 14 sin8_2 multi - function serial ch.8 serial data input pin (2) 47 55 63 sin9_2 multi - function serial ch.9 serial data input pin (2) 38 46 54 sot0_0 multi - function serial ch.0 serial data output pin (0) 63 77 89 sot1_0 multi - function serial ch.1 serial data output pin (0) 5 5 5 sot2_0 multi - function serial ch.2 serial data output pin (0) 40 48 56 sot3_0 multi - function serial ch.3 serial data output pin (0) 50 58 66 sot4_0 multi - function serial ch.4 serial data output pin (0) 139 171 203 sot8_0 multi - function serial ch.8 serial data output pin (0) 104 128 152 sot9_0 multi - function serial ch.9 serial data output pin (0) 110 134 158 sot10_0 multi - function serial ch.10 serial data output pin (0) 115 139 165 sot11_0 multi - function serial ch.11 serial data output pin (0) 121 145 173 sot12_0 multi - function serial ch.12 serial data output pin (0) 126 150 179 sot16_0 multi - function serial ch.16 serial data output pin (0) 68 84 98 sot17_0 multi - function serial ch.17 serial data output pin (0) 93 117 139 sot0_1 multi - function serial ch.0 serial data output pin (1) 7 7 10 sot1_1 multi - function serial ch.1 serial data output pin (1) - 21 27 sot2_1 multi - function serial ch.2 serial data output pin (1) - 154 186 sot3_1 multi - function serial ch.3 serial data output pin (1) - 164 196 sot4_1 multi - function serial ch.4 serial data output pin (1) - 25 33 sot8_1 multi - function serial ch.8 serial data output pin (1) - 71 83 sot9_1 multi - function serial ch.9 serial data output pin (1) - 107 124 sot10_1 multi - function serial ch.10 serial data output pin (1) - 79 91 sot12_1 multi - function serial ch.12 serial data output pin (1) - - 130 sot16_1 multi - function serial ch.16 serial data output pin (1) - - 137 sot17_1 multi - function serial ch.17 serial data output pin (1) - - 17 sot8_2 multi - function serial ch.8 serial data output pin (2) 49 57 65 sot9_2 multi - function serial ch.9 serial data output pin (2) 39 47 55 scl0 i 2 c ch.0 clock i/o pin 62 74 86 scl1 i 2 c ch.1 clock i/o pin 4 4 4 scl4 i 2 c ch.4 clock i/o pin 138 170 202 scl8 i 2 c ch.8 clock i/o pin 103 127 151 scl9 i 2 c ch.9 clock i/o pin 107 131 155 scl10 i 2 c ch.10 clock i/o pin 114 138 164 scl11 i 2 c ch.11 clock i/o pin 120 144 171 scl12 i 2 c ch.12 clock i/o pin 125 149 178 scl16 i 2 c ch.16 clock i/o pin 67 83 95 scl17 i 2 c ch.17 clock i/o pin 88 112 129
document number: 002- 10635 rev.** page 38 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 sda0 i 2 c ch.0 serial data i/o pin 63 77 89 sda1 i 2 c ch.1 serial data i/o pin 5 5 5 sda4 i 2 c ch.4 serial data i/o pin 139 171 203 sda8 i 2 c ch.8 serial data i/o pin 104 128 152 sda9 i 2 c ch.9 serial data i/o pin 110 134 158 sda10 i 2 c ch.10 serial data i/o pin 115 139 165 sda11 i 2 c ch.11 serial data i/o pin 121 145 173 sda12 i 2 c ch.12 serial data i/o pin 126 150 179 sda16 i 2 c ch.16 serial data i/o pin 68 84 98 sda17 i 2 c ch.17 serial data i/o pin 93 117 139 ppg0_tout0_0 base timer 0 output pin (0) 61 73 85 ppg0_tout2_0 base timer 1 output pin (0) 62 74 86 ppg1_tout0_0 base timer 2 output pin (0) 63 77 89 ppg1_tout2_0 base timer 3 output pin (0) 64 78 90 ppg2_tout0_0 base timer 4 output pin (0) 65 81 93 ppg2_tout2_0 base timer 5 output pin (0) 66 82 94 ppg3_tout0_0 base timer 6 output pin (0) 67 83 95 ppg3_tout2_0 base timer 7 output pin (0) 68 84 98 ppg4_tout0_0 base timer 8 output pin (0) 70 86 102 ppg4_tout2_0 base timer 9 output pin (0) 71 87 103 ppg5_tout0_0 base timer 10 output pin (0) 87 111 128 ppg5_tout2_0 base timer 11 output pin (0) 88 112 129 ppg6_tout0_0 base timer 12 output pin (0) 100 124 148 ppg6_tout2_0 base timer 13 output pin (0) 101 125 149 ppg7_tout0_0 base timer 14 output pin (0) 102 126 150 ppg7_tout2_0 base timer 15 output pin (0) 103 127 151 ppg8_tout0_0 base timer 16 output pin (0) 104 128 152 ppg8_tout2_0 base timer 17 output pin (0) 105 129 153 ppg9_tout0_0 base timer 18 output pin (0) 106 130 154 ppg9_tout2_0 base timer 19 output pin (0) 107 131 155 ppg10_tout0_0 base timer 20 output pin (0) 110 134 158 ppg10_tout2_0 base timer 21 output pin (0) 111 135 160 ppg11_tout0_0 base timer 22 output pin (0) 112 136 161 ppg11_tout2_0 base timer 23 output pin (0) 113 137 162 ppg12_tout0_0 base timer 24 output pin (0) 115 139 165 ppg12_tout2_0 base timer 25 output pin (0) 116 140 166 ppg13_tout0_0 base timer 26 output pin (0) 117 141 168 ppg13_tout2_0 base timer 27 output pin (0) 120 144 171 ppg14_tout0_0 base timer 28 output pin (0) 121 145 173 ppg14_tout2_0 base timer 29 output pin (0) 122 146 174 ppg15_tout0_0 base timer 30 output pin (0) 123 147 175 ppg15_tout2_0 base timer 31 output pin (0) 124 148 177 ppg0_tout0_1 base timer 1 output pin (1) 8 8 11 ppg0_tout2_1 base timer 1 output pin (1) 9 9 12 ppg1_tout0_1 base timer 2 output pin (1) 10 10 13 ppg1_tout2_1 base timer 3 output pin (1) 11 11 14 ppg2_tout0_1 base timer 4 output pin (1) 12 12 18 ppg2_tout2_1 base timer 5 output pin (1) 13 13 19 ppg3_tout0_1 base timer 6 output pin (1) 14 14 20
document number: 002- 10635 rev.** page 39 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 ppg3_tout2_1 base timer 7 output pin (1) 15 15 21 ppg4_tout0_1 base timer 8 output pin (1) - 19 25 ppg4_tout2_1 base timer 9 output pin (1) - 20 26 ppg5_tout0_1 base timer 11 output pin (1) - 21 27 ppg5_tout2_1 base timer 11 output pin (1) - 22 28 ppg6_tout0_1 base timer 12 output pin (1) - 69 81 ppg6_tout2_1 base timer 13 output pin (1) - 70 82 ppg7_tout0_1 base timer 14 output pin (1) - 71 83 ppg7_tout2_1 base timer 15 output pin (1) - 72 84 ppg8_tout0_1 base timer 16 output pin (1) - 75 87 ppg8_tout2_1 base timer 17 output pin (1) - 76 88 ppg9_tout0_1 base timer 18 output pin (1) - 79 91 ppg9_tout2_1 base timer 19 output pin (1) - 80 92 ppg10_tout0_1 base timer 21 output pin (1) - 98 114 ppg10_tout2_1 base timer 21 output pin (1) - 99 115 ppg11_tout0_1 base timer 22 output pin (1) - 105 122 ppg11_tout2_1 base timer 23 output pin (1) - 106 123 ppg12_tout0_1 base timer 24 output pin (1) - 154 186 ppg12_tout2_1 base timer 25 output pin (1) - 155 187 ppg13_tout0_1 base timer 26 output pin (1) - 156 188 ppg13_tout2_1 base timer 27 output pin (1) - 157 189 ppg14_tout0_1 base timer 28 output pin (1) 130 158 190 ppg14_tout2_1 base timer 29 output pin (1) - 162 194 ppg15_tout0_1 base timer 31 output pin (1) - 163 195 ppg15_tout2_1 base timer 31 output pin (1) - 164 196 ppg0/1/2/3/4/5_tin1_0 base timer 0/2/4/6/8/10 input pin (0) 93 117 139 ppg6/7/8/9/10/11_tin1_0 base timer 12/14/16/18/20/22 input pin (0) 114 138 164 ppg12/13/14/15_tin1_0 base timer 24/26/28/30 input pin (0) 125 149 178 ppg0/1/2/3/4/5_tin1_1 base timer 0/2/4/6/8/10 input pin (1) - 23 29 ppg6/7/8/9/10/11_tin1_1 base timer 12/14/16/18/20/22 input pin (1) - 107 124 ppg12/13/14/15_tin1_1 base timer 24/26/28/30 input pin (1) - 165 197 wot rtc overflow output pin 93 117 139 pwm1m0 smc ch.0 output pin 101 125 149 pwm1m1 smc ch.1 output pin 105 129 153 pwm1m2 smc ch.2 output pin 111 135 160 pwm1m3 smc ch.3 output pin 115 139 165 pwm1m4 smc ch.4 output pin 121 145 173 pwm1m5 smc ch.5 output pin 125 149 178 pwm1p0 smc ch.0 output pin 100 124 148 pwm1p1 smc ch.1 output pin 104 128 152 pwm1p2 smc ch.2 output pin 110 134 158 pwm1p3 smc ch.3 output pin 114 138 164 pwm1p4 smc ch.4 output pin 120 144 171 pwm1p5 smc ch.5 output pin 124 148 177 pwm2m0 smc ch.0 output pin 103 127 151 pwm2m1 smc ch.1 output pin 107 131 155 pwm2m2 smc ch.2 output pin 113 137 162 pwm2m3 smc ch.3 output pin 117 141 168 pwm2m4 smc ch.4 output pin 123 147 175
document number: 002- 10635 rev.** page 40 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 pwm2m5 smc ch.5 output pin 127 151 181 pwm2p0 smc ch.0 output pin 102 126 150 pwm2p1 smc ch.1 output pin 106 130 154 pwm2p2 smc ch.2 output pin 112 136 161 pwm2p3 smc ch.3 output pin 116 140 166 pwm2p4 smc ch.4 output pin 122 146 174 pwm2p5 smc ch.5 output pin 126 150 179 ocu0_otd0_0 output compare 0 ch.0 output pin (0) 61 73 85 ocu0_otd1_0 output compare 0 ch.1 output pin (0) 62 74 86 ocu1_otd0_0 output compare 1 ch.0 output pin (0) 65 81 93 ocu1_otd1_0 output compare 1 ch.1 output pin (0) 66 82 94 ocu2_otd0_0 output compare 2 ch.0 output pin (0) 67 83 95 ocu2_otd1_0 output compare 2 ch.1 output pin (0) 68 84 98 ocu8_otd0 _0 output compare 8 ch.0 output pin (0) 70 86 102 ocu8_otd1_0 output compare 8 ch.1 output pin (0) 71 87 103 ocu9_otd0_0 output compare 9 ch.0 output pin (0) 81 97 113 ocu9_otd1_0 output compare 9 ch.1 output pin (0) 87 111 128 ocu10_otd0_0 output compare 10 ch.0 output pin (0) 88 112 129 ocu10_otd1_0 output compare 10 ch.1 output pin (0) 93 117 139 ocu0_otd0_1 output compare 0 ch.0 output pin (1) - 69 81 ocu0_otd1_1 output compare 0 ch.1 output pin (1) - 70 82 ocu1_otd0_1 output compare 1 ch.0 output pin (1) - 71 83 ocu1_otd1_1 output compare 1 ch.1 output pin (1) - 72 84 ocu2_otd0_1 output compare 2 ch.0 output pin (1) - 75 87 ocu2_otd1_1 output compare 2 ch.1 output pin (1) - 76 88 ocu8_otd0_1 output compare 8 ch.0 output pin (1) - 79 91 ocu8_otd1_1 output compare 8 ch.1 output pin (1) - 80 92 ocu9_otd0_1 output compare 9 ch.0 output pin (1) - 98 114 ocu9_otd1_1 output compare 9 ch.1 output pin (1) - 99 115 ocu10_otd0_1 output compare 10 ch.0 output pin (1) - 105 122 ocu10_otd1_1 output compare 10 ch.1 output pin (1) - 106 123 icu0_in0_0 input capture 0 ch.0 input pin (0) 61 73 85 icu0_in1_0 input capture 0 ch.1 input pin (0) 62 74 86 icu1_in0_0 input capture 1 ch.0 input pin (0) 63 77 89 icu1_in1_0 input capture 1 ch.1 input pin (0) 64 78 90 icu2_in0_0 input capture 2 ch.0 input pin (0) 65 81 93 icu2_in1_0 input capture 2 ch.1 input pin (0) 66 82 94 icu8_in0_0 input capture 8 ch.0 input pin (0) 67 83 95 icu8_in1_0 input capture 8 ch.1 input pin (0) 68 84 98 icu9_in0_0 input capture 9 ch.0 input pin (0) 70 86 102 icu9_in1_0 input capture 9 ch.1 input pin (0) 71 87 103 icu10_in0_0 input capture 10 ch.0 input pin (0) 87 111 128 icu10_in1_0 input capture 10 ch.1 input pin (0) 88 112 129 icu0_in0_1 input capture 0 ch.0 input pin (1) - 69 81 icu0_in1_1 input capture 0 ch.1 input pin (1) - 70 82 icu1_in0_1 input capture 1 ch.0 input pin (1) - 71 83 icu1_in1_1 input capture 1 ch.1 input pin (1) - 72 84 icu2_in0_1 input capture 2 ch.0 input pin (1) - 75 87 icu2_in1_1 input capture 2 ch.1 input pin (1) - 76 88
document number: 002- 10635 rev.** page 41 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 icu8_in0_1 input capture 8 ch.0 input pin (1) - 79 91 icu8_in1_1 input capture 8 ch.1 input pin (1) - 80 92 icu9_in0_1 input capture 9 ch.0 input pin (1) - 98 114 icu9_in1_1 input capture 9 ch.1 input pin (1) - 99 115 icu10_in0_1 input capture 10 ch.0 input pin (1) - 105 122 icu10_in1_1 input capture 10 ch.1 input pin (1) - 106 123 sga0_0 sound generator ch.0 sga output pin (0) 63 77 89 sga1_0 sound generator ch.1 sga output pin (0) 65 81 93 sga2_0 sound generator ch.2 sga output pin (0) 67 83 95 sga3_0 sound generator ch.3 sga output pin (0) 81 97 113 sga4_0 sound generator ch.4 sga output pin (0) 88 112 129 sga0_1 sound generator ch.0 sga output pin (1) - 69 81 sga1_1 sound generator ch.1 sga output pin (1) - 71 83 sga2_1 sound generator ch.2 sga output pin (1) - 75 87 sga3_1 sound generator ch.3 sga output pin (1) - 79 91 sga4_1 sound generator ch.4 sga output pin (1) - 98 114 sgo0_0 sound generator ch.0 sgo output pin (0) 64 78 90 sgo1_0 sound generator ch.1 sgo output pin (0) 66 82 94 sgo2_0 sound generator ch.2 sgo output pin (0) 68 84 98 sgo3_0 sound generator ch.3 sgo output pin (0) 87 111 128 sgo4_0 sound generator ch.4 sgo output pin (0) 93 117 139 sgo0_1 sound generator ch.0 sgo output pin (1) - 70 82 sgo1_1 sound generator ch.1 sgo output pin (1) - 72 84 sgo2_1 sound generator ch.2 sgo output pin (1) - 76 88 sgo3_1 sound generator ch.3 sgo output pin (1) - 80 92 sgo4_1 sound generator ch.4 sgo output pin (1) - 99 115 an0(al0) pcm pwm ch.0 output pin 63 77 89 an1(al1) pcm pwm ch.1 output pin 67 83 95 ap0(ah0) pcm pwm ch.0 output pin 64 78 90 ap1(ah1) pcm pwm ch.1 output pin 68 84 98 bn0(bl0) pcm pwm ch.0 output pin 61 73 85 bn1(bl1) pcm pwm ch.1 output pin 65 81 93 bp0(bh0) pcm pwm ch.0 output pin 62 74 86 bp1(bh1) pcm pwm ch.1 output pin 66 82 94 i2s0_eclk_0 i2s external clock ch.0 input pin (0) 12 12 18 i2s0_eclk_1 i2s external clock ch.0 input pin (1) - 154 186 i2s1_eclk_0 i2s external clock ch.1 input pin (0) 8 8 11 i2s0_sck_0 i2s continuous serial clock ch.0 i/o pin (0) 15 15 21 i2s0_sck_1 i2s continuous serial clock ch.0 i/o pin (1) - 157 189 i2s1_sck_0 i2s continuous serial clock ch.1 i/o pin (0) 11 11 14 i2s0_sd_0 i2s serial data ch.0 i/o pin (0) 13 13 19 i2s0_sd_1 i2s serial data ch.0 i/o pin (1) - 155 187 i2s1_sd_0 i2s serial data ch.1 i/o pin (0) 9 9 12 i2s0_ws_0 i2s word select ch.0 i/o pin (0) 14 14 20 i2s0_ws_1 i2s word select ch.0 i/o pin (1) - 156 188 i2s1_ws_0 i2s word select ch.1 i/o pin (0) 10 10 13 c_l audio dac external capacity connection output pin (l) 34 42 50 c_r audio dac external capacity connection output pin (r) 30 38 46
document number: 002- 10635 rev.** page 42 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 dac_l audio dac output pin (l) 33 41 49 dac_r audio dac output pin (r) 29 37 45 frt0/1/2/3_text free - run timer ch.0/1/2/3 clock input pin 61 73 85 frt4/8/9/10_text free - run timer ch.4/8/9/10 clock input pin 62 74 86 tin0_0 reload timer ch.0 event input pin (0) 61 73 85 tin1_0 reload timer ch.1 event input pin (0) 63 77 89 tin16_0 reload timer ch.16 event input pin (0) 65 81 93 tin17_0 reload timer ch.17 event input pin (0) 70 86 102 tin48_0 reload timer ch.48 event input pin (0) 81 97 113 tin49_0 reload timer ch.49 event input pin (0) 88 112 129 tin0_1 reload timer ch.0 event input pin (0) - 69 81 tin1_1 reload timer ch.1 event input pin (1) - 71 83 tin16_1 reload timer ch.16 event input pin (1) - 75 87 tin17_1 reload timer ch.17 event input pin (1) - 79 91 tin48_1 reload timer ch.48 event input pin (1) - 98 114 tin49_1 reload timer ch.49 event input pin (1) - 107 124 tot0_0 reload timer ch.0 output pin (0) 62 74 86 tot1_0 reload timer ch.1 output pin (0) 64 78 90 tot16_0 reload timer ch.16 output pin (0) 66 82 94 tot17_0 reload timer ch.17 output pin (0) 71 87 103 tot48_0 reload timer ch.48 output pin (0) 87 111 128 tot49_0 reload timer ch.49 output pin (0) 93 117 139 tot0_1 reload timer ch.0 output pin (1) - 70 82 tot1_1 reload timer ch.1 output pin (1) - 72 84 tot16_1 reload timer ch.16 output pin (1) - 76 88 tot17_1 reload timer ch.17 output pin (1) - 80 92 tot48_1 reload timer ch.48 output pin (1) - 99 115 tot49_1 reload timer ch.49 output pin (1) - 108 125 ain8 up/down counter ain input pin ch.8 61 73 85 ain9 up/down counter ain input pin ch.9 64 78 90 bin8 up/down counter bin input pin ch.8 62 74 86 bin9 up/down counter bin input pin ch.9 65 81 93 zin8 up/down counter zin input pin ch.8 63 77 89 zin9 up/down counter zin input pin ch.9 66 82 94 rxd0_0 ethernet pin (0) 47 55 63 rxd1_0 ethernet pin (0) 48 56 64 rxd2_0 ethernet pin (0) 49 57 65 rxd3_0 ethernet pin (0) 50 58 66 txd0_0 ethernet pin (0) 39 47 55 txd1_0 ethernet pin (0) 40 48 56 txd2_0 ethernet pin (0) 41 49 57 txd3_0 ethernet pin (0) 42 50 58 col_0 ethernet pin (0) 55 63 71 crs_0 ethernet pin (0) 56 64 72 rxer_0 ethernet pin (0) 23 31 39 rxdv_0 ethernet pin (0) 24 32 40 rxclk_0 ethernet pin (0) 22 30 38 txer_0 ethernet pin (0) 44 52 60 txen_0 ethernet pin (0) 38 46 54
document number: 002- 10635 rev.** page 43 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 txclk_0 ethernet pin (0) 25 33 41 mdc_0 ethernet pin (0) 54 62 70 mdio_0 ethernet pin (0) 51 59 67 rxd0_1 ethernet pin (1) - 23 29 rxd1_1 ethernet pin (1) - - 30 rxd2_1 ethernet pin (1) - - 31 rxd3_1 ethernet pin (1) - 24 32 txd0_1 ethernet pin (1) - - 17 txd1_1 ethernet pin (1) - 19 25 txd2_1 ethernet pin (1) - 20 26 txd3_1 ethernet pin (1) - 21 27 col_1 ethernet pin (1) 24 32 40 crs_1 ethernet pin (1) 25 33 41 rxer_1 ethernet pin (1) - - 7 rxdv_1 ethernet pin (1) - - 8 rxclk_1 ethernet pin (1) - - 6 txer_1 ethernet pin (1) - 22 28 txen_1 ethernet pin (1) - - 16 txclk_1 ethernet pin (1) - - 15 mdc_1 ethernet pin (1) 23 31 39 mdio_1 ethernet pin (1) - 25 33 mlbclk medialb pin 54 62 70 mlbdat medialb pin 56 64 72 mlbsig medialb pin 55 63 71 m_sclk0 mcu hs - spi clock output pin 44 52 60 m_sdata0_0 mcu hs - spi0 data 0 i/o pin 38 46 54 m_sdata0_1 mcu hs - spi0 data 1 i/o pin 40 48 56 m_sdata0_2 mcu hs - spi0 data 2 i/o pin 39 47 55 m_sdata0_3 mcu hs - spi0 data 3 i/o pin 42 50 58 m_sdata1_0 mcu hs - spi1 data 0 i/o pin 47 55 63 m_sdata1_1 mcu hs - spi1 data 1 i/o pin 49 57 65 m_sdata1_2 mcu hs - spi1 data 2 i/o pin 48 56 64 m_sdata1_3 mcu hs - spi1 data 3 i/o pin 51 59 67 m_ssel0 mcu hs - spi0 select output pin 41 49 57 m_ssel1 mcu hs - spi1 select output pin 50 58 66 m_ck mcu hyper bus clock output pin 44 52 60 m_cs# _ 1 mcu hyper bus select 1 output pin 42 50 58 m_cs# _ 2 mcu hyper bus select 2 output pin 54 62 70 m_dq0 mcu hyper bus data 0 pin 41 49 57 m_dq1 mcu hyper bus data 1 pin 40 48 56 m_dq2 mcu hyper bus data 2 pin 39 47 55 m_dq3 mcu hyper bus data 3 pin 38 46 54 m_dq4 mcu hyper bus data 4 pin 48 56 64 m_dq5 mcu hyper bus data 5 pin 49 57 65 m_dq6 mcu hyper bus data 6 pin 50 58 66 m_dq7 mcu hyper bus data 7 pin 51 59 67 m_rwds mcu hyper bus rwds 47 55 63 com0 lcdc segment(duty) common output pin 15 15 21 com1 lcdc segment(duty) common output pin 19 26 34
document number: 002- 10635 rev.** page 44 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 com2 lcdc segment(duty) common output pin 20 27 35 com3 lcdc segment(duty) common output pin 21 28 36 seg0 lcdc segment(duty) output pin - 154 186 seg1 lcdc segment(duty) output pin - 155 187 seg2 lcdc segment(duty) output pin - 156 188 seg3 lcdc segment(duty) output pin - 157 189 seg4 lcdc segment(duty) output pin 130 158 190 seg5 lcdc segment(duty) output pin - 162 194 seg6 lcdc segment(duty) output pin - 163 195 seg7 lcdc segment(duty) output pin - 164 196 seg8 lcdc segment(duty) output pin - 165 197 seg9 lcdc segment(duty) output pin 134 166 198 seg10 lcdc segment(duty) output pin 135 167 199 seg11 lcdc segment(duty) output pin 136 168 200 seg12 lcdc segment(duty) output pin 137 169 201 seg13 lcdc segment(duty) output pin 138 170 202 seg14 lcdc segment(duty) output pin 139 171 203 seg15 lcdc segment(duty) output pin 140 172 204 seg16 lcdc segment(duty) output pin 141 173 205 seg17 lcdc segment(duty) output pin 142 174 206 seg18 lcdc segment(duty) output pin 143 175 207 seg19 lcdc segment(duty) output pin 2 2 2 seg20 lcdc segment(duty) output pin 3 3 3 seg21 lcdc segment(duty) output pin 4 4 4 seg22 lcdc segment(duty) output pin 5 5 5 seg23 lcdc segment(duty/static) output pin 6 6 9 seg24 lcdc segment(duty/static) output pin 7 7 10 seg25 lcdc segment(duty/static) output pin 8 8 11 seg26 lcdc segment(duty/static) output pin 9 9 12 seg27 lcdc segment(duty/static) output pin 10 10 13 seg28 lcdc segment(duty/static) output pin 11 11 14 seg29 lcdc segment(duty/static) output pin 12 12 18 seg30 lcdc segment(duty/static) output pin 13 13 19 seg31 lcdc segment(duty/static) output pin 14 14 20 v0 lcdc reference voltage v0 input pin 22 30 38 v1 lcdc reference voltage v1 input pin 23 31 39 v2 lcdc reference voltage v2 input pin 24 32 40 v3 lcdc reference voltage v3 input pin 25 33 41 dsp0_clk _0 display 0 clock output pin 136 168 200 dsp0_en _0 display 0 data enable output pin 130 158 190 dsp0_vsync_0 display 0 vertical synchronization output pin 135 167 199 dsp0_hsync_0 display 0 horizontal synchronization output pin 134 166 198 dsp0_r0_0 display 0 rgb color output pin (0) 137 169 201 dsp0_r1_0 display 0 rgb color output pin (0) 138 170 202 dsp0_r2_0 display 0 rgb color output pin (0) 139 171 203 dsp0_r3_0 display 0 rgb color output pin (0) 140 172 204 dsp0_r4_0 display 0 rgb color output pin (0) 141 173 205 dsp0_r5_0 display 0 rgb color output pin (0) 142 174 206 dsp0_r6_0 display 0 rgb color output pin (0) 143 175 207
document number: 002- 10635 rev.** page 45 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 dsp0_r7_0 display 0 rgb color output pin (0) 2 2 2 dsp0_g0_0 display 0 rgb color output pin (0) 3 3 3 dsp0_g1_0 display 0 rgb color output pin (0) 4 4 4 dsp0_g2_0 display 0 rgb color output pin (0) 5 5 5 dsp0_g3_0 display 0 rgb color output pin (0) 6 6 9 dsp0_g4_0 display 0 rgb color output pin (0) 7 7 10 dsp0_g5_0 display 0 rgb color output pin (0) 8 8 11 dsp0_g6_0 display 0 rgb color output pin (0) 9 9 12 dsp0_g7_0 display 0 rgb color output pin (0) 10 10 13 dsp0_b0_0 display 0 rgb color output pin (0) 11 11 14 dsp0_b1_0 display 0 rgb color output pin (0) 12 12 18 dsp0_b2_0 display 0 rgb color output pin (0) 13 13 19 dsp0_b3_0 display 0 rgb color output pin (0) 14 14 20 dsp0_b4_0 display 0 rgb color output pin (0) 15 15 21 dsp0_b5_0 display 0 rgb color output pin (0) 19 26 34 dsp0_b6_0 display 0 rgb color output pin (0) 20 27 35 dsp0_b7_0 display 0 rgb color output pin (0) 22 30 38 dsp0_b7_1 display 0 rgb color output pin (1) 21 28 36 lcdd0 lcd bus if data i/o pin 139 171 203 lcdd1 lcd bus if data i/o pin 140 172 204 lcdd2 lcd bus if data i/o pin 141 173 205 lcdd3 lcd bus if data i/o pin 142 174 206 lcdd4 lcd bus if data i/o pin 143 175 207 lcdd5 lcd bus if data i/o pin 2 2 2 lcdd6 lcd bus if data i/o pin 3 3 3 lcdd7 lcd bus if data i/o pin 4 4 4 lcdd8 lcd bus if data i/o pin 5 5 5 lcdd9 lcd bus if data i/o pin 6 6 9 lcdd10 lcd bus if data i/o pin 7 7 10 lcdd11 lcd bus if data i/o pin 8 8 11 lcdd12 lcd bus if data i/o pin 9 9 12 lcdd13 lcd bus if data i/o pin 10 10 13 lcdd14 lcd bus if data i/o pin 11 11 14 lcdd15 lcd bus if data i/o pin 12 12 18 lcdd16 lcd bus if data i/o pin 13 13 19 lcdd17 lcd bus if data i/o pin 14 14 20 cs# lcd bus if chip select output pin 15 15 21 wr# lcd bus if write enable output pin 19 26 34 rd# lcd bus if read enable output pin 20 27 35 rs lcd bus if register select output pin 23 31 39 te lcd bus if tearing effect input pin 25 33 41 res# lcd bus if reset control output pin 24 32 40 arh0_aic0_dnclk apix output pin 11 11 14 arh0_aic0_dndata0 apix output pin 21 28 36 arh0_aic0_dndata1 apix output pin 12 12 18 arh0_aic0_rck apix input pin 23 31 39 arh0_aic0_rda0 apix input pin 25 33 41 arh0_aic0_rda1 apix input pin 24 32 40 arh0_aic0_tcki apix input pin 11 11 14
document number: 002- 10635 rev.** page 46 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 arh0_aic0_tda0 apix output pin 21 28 36 arh0_aic0_tda1 apix output pin 12 12 18 arh0_aic0_upclk apix input pin 23 31 39 arh0_aic0_updata0 apix input pin 25 33 41 arh0_aic0_updata1 apix input pin 24 32 40 arh0_aic0_dbg_out_0 apix output pin 14 14 20 arh0_aic0_dbg_out_1 apix output pin 13 13 19 arh0_aic0_dbg_select apix input pin 15 15 21 arh0_aic1_dnclk apix output pin 3 3 3 arh0_aic1_dndata0 apix output pin 7 7 10 arh0_aic1_dndata1 apix output pin 4 4 4 arh0_aic1_rck apix input pin 8 8 11 arh0_aic1_rda0 apix input pin 10 10 13 arh0_aic1_rda1 apix input pin 9 9 12 arh0_aic1_tcki apix input pin 3 3 3 arh0_aic1_tda0 apix output pin 7 7 10 arh0_aic1_tda1 apix output pin 4 4 4 arh0_aic1_upclk apix input pin 8 8 11 arh0_aic1_updata0 apix input pin 10 10 13 arh0_aic1_updata1 apix input pin 9 9 12 arh0_aic1_dbg_out_0 apix output pin 6 6 9 arh0_aic1_dbg_out_1 apix output pin 5 5 5 arh0_aic1_dbg_select apix input pin 19 26 34 indicator0_0 indicator pwm output pin 0 ( it can also obtained from indicator0_1) 70 86 102 indicator0_1 indicator pwm output pin 1 (it can also obtained from indicator0_0) 88 112 129 sysc0_clk_0 clock output pin (0) 93 117 139 sysc0_clk_1 system clock output pin (1) 87 111 128 mad0 external bus pin 143 175 207 mad1 external bus pin mad2 external bus pin mad3 external bus pin 4 4 4 mad4 external bus pin 5 5 5 mad5 external bus pin 9 mad6 external bus pin 7 7 10 mad7 external bus pin 8 8 11 mad8 external bus pin 9 9 12 mad9 external bus pin 10 10 13 mad10 external bus pin 11 11 14 mad11 external bus pin 12 12 18 mad12 external bus pin 13 13 19 mad13 external bus pin 14 14 20 mad14 external bus pin 15 15 21 mad15 external bus pin 19 25 mad16 external bus pin 20 mad17 external bus pin 21 27 mad18 external bus pin 28 mad19 external bus pin 29 mad20 external bus pin 24
document number: 002- 10635 rev.** page 47 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 mad21 external bus pin - 25 33 mdata0 external bus pin 135 167 199 mdata1 external bus pin 136 168 200 mdata2 external bus pin 137 169 201 mdata3 external bus pin 138 170 202 mdata4 external bus pin 139 171 203 mdata5 external bus pin 140 172 204 mdata6 external bus pin 141 173 205 mdata7 external bus pin 142 174 206 mdata8 external bus pin - 154 186 mdata9 external bus pin - 155 187 mdata10 external bus pin - 156 188 mdata 11 external bus pin - 157 189 mdata12 external bus pin - 162 194 mdata13 external bus pin - 163 195 mdata14 external bus pin - 164 196 mdata15 external bus pin - 165 197 mclk external bus pin 21 28 36 moex external bus pin 19 26 34 mwex external bus pin 20 27 35 mdqm0 external bus pin 22 30 38 mdqm1 external bus pin - 29 37 mcsx0 external bus pin 130 158 190 mcsx1 external bus pin 134 166 198 mcsx2 external bus pin 23 31 39 mcsx3 external bus pin 24 32 40 mrdy external bus pin 25 33 41 p0_00 general - purpose i/o port 2 2 2 p0_01 general - purpose i/o port 3 3 3 p0_02 general - purpose i/o port 4 4 4 p0_03 general - purpose i/o port 5 5 5 p0_04 general - purpose i/o port 6 6 9 p0_05 general - purpose i/o port 7 7 10 p0_06 general - purpose i/o port 8 8 11 p0_07 general - purpose i/o port 9 9 12 p0_08 general - purpose i/o port 10 10 13 p0_09 general - purpose i/o port 11 11 14 p0_10 general - purpose i/o port 12 12 18 p0_11 general - purpose i/o port 13 13 19 p0_12 general - purpose i/o port 14 14 20 p0_13 general - purpose i/o port 15 15 21 p0_14 general - purpose i/o port 19 26 34 p0_15 general - purpose i/o port 20 27 35 p0_16 general - purpose i/o port 21 28 36 p0_17 general - purpose i/o port 22 30 38 p0_18 general - purpose i/o port 23 31 39 p0_19 general - purpose i/o port 24 32 40 p0_20 general - purpose input port 25 33 41 p0_21 general - purpose i/o port 38 46 54
document number: 002- 10635 rev.** page 48 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 p0_22 general - purpose i/o port 39 47 55 p0_23 general - purpose i/o port 40 48 56 p0_24 general - purpose i/o port 41 49 57 p0_25 general - purpose i/o port 42 50 58 p0_26 general - purpose i/o port 44 52 60 p0_27 general - purpose i/o port 47 55 63 p0_28 general - purpose i/o port 48 56 64 p0_29 general - purpose i/o port 49 57 65 p0_30 general - purpose i/o port 50 58 66 p0_31 general - purpose i/o port 51 59 67 p1_00 general - purpose i/o port 54 62 70 p1_01 general - purpose i/o port 55 63 71 p1_02 general - purpose i/o port 56 64 72 p1_03 general - purpose i/o port 61 73 85 p1_04 general - purpose i/o port 62 74 86 p1_05 general - purpose i/o port 63 77 89 p1_06 general - purpose i/o port 64 78 90 p1_07 general - purpose i/o port 65 81 93 p1_08 general - purpose i/o port 66 82 94 p1_09 general - purpose i/o port 67 83 95 p1_10 general - purpose i/o port 68 84 98 p1_11 general - purpose i/o port 70 86 102 p1_12 general - purpose i/o port 71 87 103 p1_13 general - purpose i/o port 81 97 113 p1_14 general - purpose i/o port 87 111 128 p1_15 general - purpose i/o port 88 112 129 p1_16 general - purpose i/o port 93 117 139 p1_17 general - purpose i/o port 100 124 148 p1_18 general - purpose i/o port 101 125 149 p1_19 general - purpose i/o port 102 126 150 p1_20 general - purpose i/o port 103 127 151 p1_21 general - purpose i/o port 104 128 152 p1_22 general - purpose i/o port 105 129 153 p1_23 general - purpose i/o port 106 130 154 p1_24 general - purpose i/o port 107 131 155 p1_25 general - purpose i/o port 110 134 158 p1_26 general - purpose i/o port 111 135 160 p1_27 general - purpose i/o port 112 136 161 p1_28 general - purpose i/o port 113 137 162 p1_29 general - purpose i/o port 114 138 164 p1_30 general - purpose i/o port 115 139 165 p1_31 general - purpose i/o port 116 140 166 p2_00 general - purpose i/o port 117 141 168 p2_01 general - purpose i/o port 120 144 171 p2_02 general - purpose i/o port 121 145 173 p2_03 general - purpose i/o port 122 146 174 p2_04 general - purpose i/o port 123 147 175 p2_05 general - purpose i/o port 124 148 177 p2_06 general - purpose i/o port 125 149 178
document number: 002- 10635 rev.** page 49 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 p2_07 general - purpose i/o port 126 150 179 p2_08 general - purpose i/o port 127 151 181 p2_09 general - purpose i/o port 130 158 190 p2_10 general - purpose i/o port 134 166 198 p2_11 general - purpose i/o port 135 167 199 p2_12 general - purpose i/o port 136 168 200 p2_13 general - purpose i/o port 137 169 201 p2_14 general - purpose i/o port 138 170 202 p2_15 general - purpose i/o port 139 171 203 p2_16 general - purpose i/o port 140 172 204 p2_17 general - purpose i/o port 141 173 205 p2_18 general - purpose i/o port 142 174 206 p2_19 general - purpose i/o port 143 175 207 p3_00 general - purpose i/o port - 19 25 p3_01 general - purpose i/o port - 20 26 p3_02 general - purpose i/o port - 21 27 p3_03 general - purpose i/o port - 22 28 p3_04 general - purpose i/o port - 23 29 p3_05 general - purpose i/o port - 24 32 p3_06 general - purpose i/o port - 25 33 p3_07 general - purpose i/o port - 29 37 p3_08 general - purpose i/o port - 69 81 p3_09 general - purpose i/o port - 70 82 p3_10 general - purpose i/o port - 71 83 p3_11 general - purpose i/o port - 72 84 p3_12 general - purpose i/o port - 75 87 p3_13 general - purpose i/o port - 76 88 p3_14 general - purpose i/o port - 79 91 p3_15 general - purpose i/o port - 80 92 p3_16 general - purpose i/o port - 98 114 p3_17 general - purpose i/o port - 99 115 p3_18 general - purpose i/o port - 105 122 p3_19 general - purpose i/o port - 106 123 p3_20 general - purpose i/o port - 107 124 p3_21 general - purpose i/o port - 108 125 p3_22 general - purpose i/o port - 109 126 p3_23 general - purpose i/o port - 110 127 p3_24 general - purpose i/o port - 154 186 p3_25 general - purpose i/o port - 155 187 p3_26 general - purpose i/o port - 156 188 p3_27 general - purpose i/o port - 157 189 p3_28 general - purpose i/o port - 162 194 p3_29 general - purpose i/o port - 163 195 p3_30 general - purpose i/o port - 164 196 p3_31 general - purpose i/o port - 165 197 p4_00 general - purpose i/o port - - 6 p4_01 general - purpose i/o port - - 7 p4_02 general - purpose i/o port - - 8 p4_03 general - purpose i/o port - - 15
document number: 002- 10635 rev.** page 50 of 247 s6j33 10/20/30/40 series preliminar port name description package pin number remark teqfp 144 teqfp 176 teqfp 208 p4_04 general - purpose i/o port - - 16 p4_05 general - purpose i/o port - - 17 p4_06 general - purpose i/o port - - 30 p4_07 general - purpose i/o port - - 31 p4_08 general - purpose i/o port - - 77 p4_09 general - purpose i/o port - - 78 p4_10 general - purpose i/o port - - 79 p4_11 general - purpose i/o port - - 80 p4_12 general - purpose i/o port - - 96 p4_13 general - purpose i/o port - - 97 p4_14 general - purpose i/o port - - 99 p4_15 general - purpose i/o port - - 100 p4_16 general - purpose i/o port - - 116 p4_17 general - purpose i/o port - - 130 p4_18 general - purpose i/o port - - 131 p4_19 general - purpose i/o port - - 136 p4_20 general - purpose i/o port - - 137 p4_21 general - purpose i/o port - - 138 p4_22 general - purpose i/o port - - 140 p4_23 general - purpose i/o port - - 141 p4_24 general - purpose i/o port - - 159 p4_25 general - purpose i/o port - - 163 p4_26 general - purpose i/o port - - 167 p4_27 general - purpose i/o port - - 172 p4_28 general - purpose i/o port - - 176 p4_29 general - purpose i/o port - - 180 p4_30 general - purpose i/o port - - 184 p4_31 general - purpose i/o port - - 185 6.2 remark note s : ? the port description list shows the port function of description which is mounted and supported on the product. the function which is not described in this table is not supported and assured. ? see the function list of the product as well.
document number: 002- 10635 rev.** page 51 of 247 s6j33 10/20/30/40 series preliminar 7. port configuration 7.1 resource input configuration module the resource input configuration module (ric) is a function to select input from an external or output from another internal resource as resource input. a resource which supports either a port input relocation or a resource inputs from the other resource has its ric_resin register to configure r esource input configuration. s633 register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin000 (0x0000) sin16 ressel (0 -7) - - - - - - - - ressel (8 - - - - - - - - - portse l (0 -7) p1_08 p4_19 - - - - - - portse l (8 - - - - - - - - - ric_re sin001 (0x0002) sck16 ressel (0 -7) - - - - - - - - ressel (8 - - - - - - - - - portse l (0 -7) p1_09 p4_21 - - - - - - portse l (8 - - - - - - - - - ric_re sin002 (0x0004) scl16 ressel (0 -7) 80ns filter disable 80ns filter enable - - - - - - ressel (8 - - - - - - - - - portse l (0 -7) - - - - - - - - portse l (8 - - - - - - - - - ric_re sin003 (0x0006) sda16 ressel (0 -7) 80ns filter disable 80ns filter enable - - - - - - ressel (8 - - - - - - - - - portse l (0 -7) - - - - - - - - portse l (8 - - - - - - - - -
document number: 002- 10635 rev.** page 52 of 2 47 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin004 (0x0008) mfs16_ trigge r ressel (0 - 2 tot49 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin005 (0x000a) scs16 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p4_23 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin007 (0x000e) sin17 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p0_09 - - - - - - portse (8 -15) - - - - - - - - ric_re sin008 (0x0010) sck17 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p4_04 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin009 (0x0012) scl17 ressel (0 -7) 80ns noise filter disable q noise filter enable - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 53 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin010 (0x0014) sda17 ressel (0 -7) 80ns noise filter disable q noise filter enable - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin011 (0x0016) mfs17_ trigge r ressel (0 - 2 tot49 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin012 (0x0018) scs17 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p4_03 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin021 (0x002a) sin0 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p0_04 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin022 (0x002c) sck0 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p0_06 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 54 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin023 (0x002e) scl0 ressel (0 -7) 80ns noise filter disable q noise filter enable - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin024 (0x0030) sda0 ressel (0 -7) 80ns noise filter disable q noise filter enable - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin025 (0x0032) mfs0_t rigger ressel (0 - 2 tot1 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin026 (0x0034) scs0 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p0_07 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin028 (0x0038) sin1 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_00 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 55 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin029 (0x003a) sck1 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_01 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin030 (0x003c) scl1 ressel (0 -7) 80ns noise filter disable q noise filter enable - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin031 (0x003e) sda1 ressel (0 -7) 80ns noise filter disable q noise filter enable - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin032 (0x0040) mfs1_t rigger ressel (0 - 2 tot1 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin033 (0x0042) scs1 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_03 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 56 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin035 (0x0046) sin2 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p4_30 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin036 (0x0048) sck2 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p4_31 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin039 (0x004e) mfs2_t rigger ressel (0 - 2 tot1 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin040 (0x0050) scs2 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_25 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 57 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin042 (0x0054) sin3 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_28 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin043 (0x0056) sck3 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_29 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 58 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin046 (0x005c) mfs3_t rigger ressel (0 - 2 tot1 - - - - - - ressel (8 -15) - - - - - - - - portse l - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin047 (0x005e) scs3 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_31 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin049 (0x0062) sin4 ressel (0 7) ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_05 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin050 (0x0064) sck4 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p0_14 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin051 (0x0066) scl4 ressel (0 -7) 80ns noise filter disable q noise filter enable - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 59 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin052 (0x0068) sda4 ressel (0 -7) 80ns noise filter disable q noise filter enable - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin053 (0x006a) mfs4_t rigger ressel (0 - 2 tot1 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin054 (0x006c) scs4 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p0_15 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin077 (0x009a) sin8 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l - 3 p3_08 p0_27 - - - - - portse l (8 -15) - - - - - - - - ric_re sin078 (0x009c) sck8 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_09 p0_28 - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 60 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin079 (0x009e) scl8 ressel (0 -7) 80ns noise filter disable q noise filter enable - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin080 (0x00a0) sda8 ressel (0 -7) 80ns noise filter disable q noise filter enable - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin081 (0x00a2) mfs8_t rigger ressel (0 - 2 tot17 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin082 (0x00a4) scs8 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_11 p0_30 - - - - - portse l (8 -15) - - - - - - - - ric_re sin084 (0x00a8) sin9 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_18 p0_21 - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 61 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin085 (0x00aa) sck9 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_19 p0_23 - - - - - portse l (8 -15) - - - - - - - - ric_re sin086 (0x00ac) scl9 ressel (0 -7) 80ns noise filter disable q noise filter enable - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin087 (0x00ae) sda9 ressel (0 -7) 80ns noise filter disable q noise filter enable - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin088 (0x00b0) mfs9_t rigger ressel (0 - 2 tot17 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin089 (0x00b2) scs9 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_21 p0_24 - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 62 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin091 (0x00b6) sin10 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_12 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin092 (0x00b8) sck10 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_13 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin093 (0x00ba) scl10 ressel (0 -7) 80ns noise filter disable q noise filter enable - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin094 (0x00bc) sda10 ressel (0 -7) 80ns noise filter disable q noise filter enable - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin095 (0x00be) mfs10_ trigge r ressel (0 - 2 tot17 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 63 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin096 (0x00c0) scs10 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_15 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin100 (0x00c8) scl11 ressel (0 -7) 80ns noise filter disable q noise filter enable - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin101 (0x00ca) sda11 ressel (0 -7) 80ns noise filter disable q noise filter enable - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin102 (0x00cc) mfs11_ trigge r ressel (0 - 2 tot17 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin105 (0x00d2) sin12 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p4_18 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 64 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin106 (0x00d4) sck12 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 -7) p2_06 p1_15 - - - - - - portse l (8 - - - - - - - - - ric_re sin107 (0x00d6) scl12 ressel (0 -7) 80ns noise filter disable q noise filter enable - - - - - - ressel (8 - - - - - - - - - portse l (0 - - - - - - - - - portse l (8 - - - - - - - - - ric_re sin108 (0x00d8) sda12 ressel (0 -7) 80ns noise filter disable q noise filter enable - - - - - - ressel (8 - - - - - - - - - portse l (0 - - - - - - - - - portse l (8 - - - - - - - - - ric_re sin109 (0x00da) mfs12_ trigge r ressel (0 - 2 tot17 - - - - - - ressel (8 - - - - - - - - - portse l (0 - - - - - - - - - portse l (8 - - - - - - - - - ric_re sin110 (0x00dc) scs12 ressel (0 - - - - - - - - - ressel (8 - - - - - - - - - portse l (0 - 3 p3_23 - - - - - - portse l (8 - - - - - - - - -
document number: 002- 10635 rev.** page 65 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin133 (0x010a) rx5 ressel (0 -7) port_ pin mcan5 _pin_a nd_tx - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_19 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin134 (0x010c) rx6 ressel (0 -7) port_ pin mcan6 _pin_a nd_tx - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_22 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin136 (0x0110) rx0 ressel (0 -7) port_ pin mcan0 _pin_a nd_tx - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_09 p4_00 - - - - - portse l (8 -15) - - - - - - - - ric_re sin137 (0x0112) rx1 ressel (0 -7) port_ pin mcan1 _pin_a nd_tx - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_11 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 66 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin138 (0x0114) rx2 ressel (0 -7) port_ pin mcan2 _pin_a nd_tx - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_14 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin139 (0x0116) rx3 ressel (0 -7) port_ pin mcan3 _pin_a nd_tx - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_16 p4_03 - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 67 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin141 (0x011a) tin48 ressel (0 - 32 3, 2 rlt49_ ufset - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_16 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin142 (0x011c) tin49 ressel (0 - 32 3, 2 rlt48_ ufset - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_20 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin144 (0x0120) tin0 ressel (0 - 32 3, 2 rlt1_u fset - ppg0_t out0 - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_08 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin145 (0x0122) tin1 ressel (0 - 32 3, 2 rlt0_u fset - ppg1_t out0 - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_10 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 68 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin160 (0x0140) tin16 ressel (0 - 32 3, 2 rlt17_ ufset - ppg6_t out0 - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_12 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin161 (0x0142) tin17 ressel (0 - 32 3, 2 rlt16_ ufset - ppg7_t out0 - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_14 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 69 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin192 (0x0180) eint0 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p0_00 p0_08 p0_20 p3_17 p2_01 p2_16 - portse l (8 -15) - - - - - - - - ric_re sin193 (0x0182) eint1 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_00 p0_09 p0_22 p4_16 p4_27 p2_17 - portse l (8 -15) - - - - - - - - ric_re sin194 (0x0184) eint2 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p4_30 p4_03 p0_23 p3_20 p2_02 p2_18 - portse l (8 -15) - - - - - - - - ric_re sin195 (0x0186) eint3 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_28 p4_04 p0_24 p3_21 p2_03 p2_19 - portse l (8 -15) - - - - - - - - ric_re sin196 (0x0188) eint4 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p0_02 p4_05 p0_25 p3_23 p2_04 - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 70 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin197 (0x018a) eint5 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p0_03 p0_10 p0_26 p4_17 p4_28 - - portse l (8 -15) - - - - - - - - ric_re sin198 (0x018c) eint6 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_09 p0_11 p0_27 p4_18 p2_06 - - portse (8 -15) - - - - - - - - ric_re sin199 (0x018e) eint7 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p4_00 p0_12 p0_29 p4_20 p2_07 - - portse l (8 -15) - - - - - - - - ric_re sin200 (0x0190) eint8 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_11 p0_13 p0_30 p4_21 p4_29 - - portse l (8 -15) - - - - - - - - ric_re sin201 (0x0192) eint9 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p4_01 p3_01 p0_31 p1_16 p2_08 - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 71 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin202 (0x0194) eint10 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p4_02 p3_02 p1_00 p4_23 p4_31 - - portse l (8 -15) - - - - - - - - ric_re sin203 (0x0196) eint11 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p0_04 p3_03 p1_01 p1_18 p3_24 - - portse l (8 -15) - - - - - - - - ric_re sin204 (0x0198) eint12 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_14 p3_04 p1_02 p1_20 p3_25 - - portse l (8 -15) - - - - - - - - ric_re sin205 (0x019a) eint13 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p0_05 p4_06 p4_08 p1_22 p3_26 - - portse (8 -15) - - - - - - - - ric_re sin206 (0x019c) eint14 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_16 p4_07 p4_09 p1_24 p3_27 - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 72 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin207 (0x019e) eint15 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p0_06 p3_05 p4_10 p1_25 p2_09 - - portse l (8 -15) - - - - - - - - ric_re sin208 (0x01a0) eint16 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p4_19 p3_06 p4_11 p4_24 p3_29 - - portse l (8 -15) - - - - - - - - ric_re sin209 (0x01a2) eint17 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_19 p0_14 p3_10 p1_26 p3_30 - - portse l (8 -15) - - - - - - - - ric_re sin210 (0x01a4) eint18 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_08 p0_15 p3_13 p1_27 p3_31 - - portse l (8 -15) - - - - - - - - ric_re sin211 (0x01a6) eint19 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_22 p0_16 p3_15 p4_25 p2_10 - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 73 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin212 (0x01a8) eint20 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_18 p3_07 p4_12 p1_29 p2_11 - - portse l (8 -15) - - - - - - - - ric_re sin213 (0x01aa) eint21 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_12 p0_17 p4_13 p1_30 p2_12 - - portse l (8 -15) - - - - - - - - ric_re sin214 (0x01ac) eint22 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p4_22 p0_18 p4_14 p1_31 p2_14 - - portse l (8 -15) - - - - - - - - ric_re sin215 (0x01ae) eint23 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l - 3 p0_07 p0_19 p4_15 p4_26 p2_15 - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 74 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin216 (0x01b0) text0 ressel (0 - 32 3, 2 tot1 ppg0_t out2 - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin217 (0x01b2) text1 ressel (0 - 32 3, 2 tot1 ppg1_t out2 - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin218 (0x01b4) text2 ressel (0 - 32 3, 2 tot1 ppg2_t out2 - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin219 (0x01b6) text3 ressel (0 - 32 3, 2 tot1 ppg3_t out2 - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin220 (0x01b8) text4 ressel (0 - 32 3, 2 tot1 ppg4_t out2 - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 75 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin224 (0x01c0) text8 ressel (0 - 32 3, / fset / 6 33 2 - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin225 (0x01c2) text9 ressel (0 - 32 3, / fset / 6 33 2 - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin226 (0x01c4) text10 ressel (0 - 32 3, / fset / 6 33 2 - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 76 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 in232 (0x01d0) ocu0_c k0 ressel (0 -7) frt0 frt1 frt2 frt3 frt4 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu0_c k1 ressel (0 - frt1 frt2 frt3 frt4 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu0_d ownb0 ressel (0 - 2 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu0_d ownb1 ressel (0 - 2 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu0_f cmd0 ressel (0 - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 77 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 in232 (0x01d0) ocu0_f cmd1 ressel (0 - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu0_m tsf0 ressel (0 - tsf tsf tsf tsf tsf - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse (8 -15) - - - - - - - - ocu0_m tsf1 ressel (0 - tsf tsf tsf tsf tsf - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu0_t 0[31:0] ressel (0 - > > > > > - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu0_t 1[31:0] ressel (0 - > > > > > - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 78 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 in232 (0x01d0) ocu0_z tsf0 ressel (0 - tsf tsf tsf tsf tsf - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu0_z tsf1 ressel (0 - tsf tsf tsf tsf tsf - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin233 (0x01d2) ocu0_m od0 ressel (0 - set 0 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse (8 -15) - - - - - - - - ric_re sin234 (0x01d4) ocu0_m od1 ressel (0 - set 0 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin235 (0x01d6) ocu1_c k0 ressel (0 - frt1 frt2 frt3 frt4 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 79 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin235 (0x01d6) ocu1_c k1 ressel (0 - frt1 frt2 frt3 frt4 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu1_d ownb0 ressel (0 - 2 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu1_d ownb1 ressel (0 - 2 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu1_f cmd0 ressel (0 - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu1_f cmd1 ressel (0 - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 80 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin235 (0x01d6) ocu1_m tsf0 ressel (0 - tsf tsf tsf tsf tsf - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu1_m tsf1 ressel (0 - tsf tsf tsf tsf tsf - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu1_t 0[31:0] ressel (0 - > > > > > - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu1_t 1[31:0] ressel (0 - > > > > > - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 81 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin236 (0x01d8) ocu1_z tsf0 ressel (0 - tsf tsf tsf tsf tsf - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu1_z tsf1 ressel (0 - tsf tsf tsf tsf tsf - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu1_m od0 ressel (0 - set 0 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 82 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin237 (0x01da) ocu1_m od1 ressel (0 - set 0 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin238 (0x01dc) ocu2_c k0 ressel (0 - frt1 frt2 frt3 frt4 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu2_c k1 ressel (0 - frt1 frt2 frt3 frt4 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu2_d ownb0 ressel (0 - 2 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 83 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin238 (0x01dc) ocu2_d ownb1 ressel (0 - 2 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu2_f cmd0 ressel (0 - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu2_f cmd1 ressel (0 - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu2_m tsf0 ressel (0 - tsf tsf tsf tsf tsf - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu2_m tsf1 ressel (0 - tsf tsf tsf tsf tsf - - - ressel (8 -15) - - - - - - - - portse l - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 84 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin238 (0x01dc) ocu2_t 0[31:0] ressel (0 - > > > > > - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu2_t 1[31:0] ressel (0 - > > > > > - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu2_z tsf0 ressel (0 - tsf tsf tsf tsf tsf - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu2_z tsf1 ressel (0 - tsf tsf tsf tsf tsf - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 85 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin239 (0x01de) ocu2_m od0 ressel (0 - set 0 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin240 (0x01e0) ocu2_m od1 ressel (0 - set 0 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 86 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin256 (0x0200) ocu8_c k0 ressel (0 - frt9 frt10 - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu8_c k1 ressel (0 - frt9 frt10 - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu8_d ownb0 ressel (0 - 2 2 2 - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse (8 -15) - - - - - - - - ocu8_d ownb1 ressel (0 - 2 2 2 - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu8_f cmd0 ressel (0 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 87 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin256 (0x0200) ocu8_f cmd1 ressel (0 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu8_m tsf0 ressel (0 - tsf tsf mtsf - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu8_m tsf1 ressel (0 - tsf tsf mtsf - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu8_t 0[31:0] ressel (0 - > > > - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu8_t 1[31:0] ressel (0 - > > > - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 88 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin256 (0x0200) ocu8_z tsf0 ressel (0 - tsf tsf ztsf - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu8_z tsf1 ressel (0 - tsf tsf ztsf - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin257 (0x0202) ocu8_m od0 ressel (0 - set 0 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 89 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin258 (0x0204) ocu8_m od1 ressel (0 - set 0 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin259 (0x0206) ocu9_c k0 ressel (0 - frt9 frt10 - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu9_c k1 ressel (0 - frt9 frt10 - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 90 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin259 (0x0206) ocu9_d ownb0 ressel (0 - 2 2 2 - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu9_d ownb1 ressel (0 - 2 2 2 - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu9_f cmd0 ressel (0 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu9_f cmd1 ressel (0 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu9_m tsf0 ressel (0 - tsf tsf mtsf - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 91 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin259 (0x0206) ocu9_m tsf1 ressel (0 - tsf tsf mtsf - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse (8 -15) - - - - - - - - ocu9_t 0[31:0] ressel (0 - > > > - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu9_t 1[31:0] ressel (0 - > > > - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu9_z tsf0 ressel (0 - tsf tsf ztsf - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu9_z tsf1 ressel (0 - tsf tsf ztsf - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 92 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin260 (0x0208) ocu9_m od0 ressel (0 - set 0 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin261 (0x020a) ocu9_m od1 ressel (0 - set 0 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 93 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin262 (0x020c) ocu10_ ck0 ressel (0 - frt9 frt10 - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu10_ ck1 ressel (0 - frt9 frt10 - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu10_ downb 0 ressel (0 - 2 2 2 - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu10_ downb 1 ressel (0 - 2 2 2 - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu10_ fcmd0 ressel (0 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 94 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin262 (0x020c) ocu10_ fcmd1 ressel (0 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu10_ mtsf0 ressel (0 - tsf tsf mtsf - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu10_ mtsf1 ressel (0 - tsf tsf mtsf - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu10_ t0[31:0] ressel (0 - > > > - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu10_ t1[31:0] ressel (0 - > > > - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 95 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin262 (0x020c) ocu10_ ztsf0 ressel (0 - tsf tsf ztsf - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ocu10_ ztsf1 ressel (0 - tsf tsf ztsf - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin263 (0x020e) ocu10_ mod0 ressel (0 - set 0 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin264 (0x0210) ocu10_ mod1 ressel (0 - set 0 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin280 (0x0230) icu0_in 0 ressel (0 - 32 3, 6/ 6 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_08 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 96 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin281 (0x0232) icu0_in 1 ressel (0 - 32 3, 6/ 6 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_09 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin282 (0x0234) icu0_t0[ 31:0] ressel (0 - > > > > > - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - icu0_t1[ 31:0] ressel (0 - > > > > > - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin283 (0x0236) icu1_in 0 ressel (0 - 32 3, 6/ 6 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_10 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin284 (0x0238) icu1_in 1 ressel (0 - 32 3, 6/ 6 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_11 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 97 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin285 (0x023a) icu1_t0[ 31:0] ressel (0 - > > > > > - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse (8 -15) - - - - - - - - icu1_t1[ 31:0] ressel (0 - > > > > > - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin286 (0x023c) icu2_in 0 ressel (0 - 32 3, 6/ 6 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_12 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin287 (0x023e) icu2_in 1 ressel (0 - 32 3, - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_13 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 98 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin288 (0x0240) icu2_t0[ 31:0] ressel (0 - > > > > > - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - icu2_t1[ 31:0] ressel (0 - > > > > > - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin304 (0x0260) icu8_in 0 ressel (0 - 32 3, 6/ 6 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_14 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin305 (0x0262) icu8_in 1 ressel (0 - 32 3, 6/ 6 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_15 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 99 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin306 (0x0264) icu8_t0[ 31:0] ressel (0 - > > > - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - icu8_t1[ 31:0] ressel (0 - > > > - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin307 (0x0266) icu9_in 0 ressel (0 - 32 3, 6 /6 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_16 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin308 (0x0268) icu9_in 1 ressel (0 - 32 3, 6 /6 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_17 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 100 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin309 (0x026a) icu9_t0[ 31:0] ressel (0 - > > > - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - icu9_t1[ 31:0] ressel (0 - > > > - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin310 (0x026c) icu10_i n0 ressel (0 - 32 3, 6 /6 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_18 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin311 (0x026e) icu10_i n1 ressel (0 - 32 3, - - - - - - - ressel (8 -15) - - - - - - - - portse l - 3 p3_19 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 101 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin312 (0x0270) icu10_t 0[31:0] ressel (0 - > > > - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - icu10_t 1[31:0] ressel (0 - > > > - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin352 (0x02c0) ain8 ressel (0 - 32 3, 2 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin353 (0x02c2) bin8 ressel (0 - 32 3, 2 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin354 (0x02c4) zin8 ressel (0 - 32 3, 2 ppg6_t out0 33 2 33 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 102 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin355 (0x02c6) ain9 ressel (0 - 32 3, 2 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin356 (0x02c8) bin9 ressel (0 - 32 3, 2 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin357 (0x02ca) zin9 ressel (0 - 32 3, 2 ppg6_t out0 33 2 33 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin376 (0x02f0) ppg0_ti n1 ressel (0 - 32 3, 2 rlt0_u fset 2 rlt0_u fset tsf 2 2 - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_04 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin377 (0x02f2) ppg0_ti n2 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 1 03 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin378 (0x02f4) ppg0_ti n3 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin379 (0x02f6) ppg1_ti n1 ressel (0 - 32 3, 2 rlt0_u fset 2 rlt0_u fset tsf 2 2 - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_04 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin380 (0x02f8) ppg1_ti n2 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin381 (0x02fa) ppg1_ti n3 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin382 (0x02fc) ppg2_ti n1 ressel (0 - 32 3, 2 rlt0_u fset 2 rlt0_u fset tsf 2 2 - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_04 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 104 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin383 (0x02fe) ppg2_ti n2 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin384 (0x0300) ppg2_ti n3 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin385 (0x0302) ppg3_ti n1 ressel (0 - 32 3, 2 rlt0_u fset 2 rlt1_u fset tsf 2 2 - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_04 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin386 (0x0304) ppg3_ti n2 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin387 (0x0306) ppg3_ti n3 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 105 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin388 (0x0308) ppg4_ti n1 ressel (0 - 32 3, 2 rlt0_u fset 2 rlt1_u fset tsf 2 2 - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_04 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin389 (0x030a) ppg4_ti n2 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin390 (0x030c) ppg4_ti n3 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin391 (0x030e) ppg5_ti n1 ressel (0 - 32 3, 2 rlt0_u fset 2 rlt1_u fset tsf 2 2 - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_04 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin392 (0x0310) ppg5_ti n2 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 106 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin393 (0x0312) ppg5_ti n3 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin394 (0x0314) ppg6_ti n1 ressel (0 7) port_ pin 2 rlt0_u fset 2 rlt16_ ufset tsf 2 2 - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_20 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin395 (0x0316) ppg6_ti n2 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin396 (0x0318) ppg6_ti n3 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin397 (0x031a) ppg7_ti n1 ressel (0 - 32 3, 2 rlt0_u fset 2 rlt16_ ufset tsf 2 2 - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_20 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 107 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin398 (0x031c) ppg7_ti n2 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin399 (0x031e) ppg7_ti n3 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin400 (0x0320) ppg8_ti n1 ressel (0 - 32 3, 2 rlt0_u fset 2 rlt16_ ufset tsf 2 2 - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_20 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin401 (0x0322) ppg8_ti n2 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin402 (0x0324) ppg8_ti n3 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 108 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin403 (0x0326) ppg9_ti n1 ressel (0 - 32 3, 2 rlt0_u fset 2 rlt17_ ufset tsf 2 2 - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_20 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin404 (0x0328) ppg9_ti n2 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin405 (0x032a) ppg9_ti n3 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin406 (0x032c) ppg10_ tin1 ressel (0 - 32 3, 2 rlt0_u fset 2 rlt17_ ufset tsf 2 2 - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_20 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin407 (0x032e) ppg10_ tin2 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 109 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin408 (0x0330) ppg10_ tin3 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin409 (0x0332) ppg11_ tin1 ressel (0 - 32 3, 2 rlt0_u fset 2 rlt17_ ufset tsf 2 2 - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_20 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin410 (0x0334) ppg11_ tin2 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin411 (0x0336) ppg11_ tin3 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin430 (0x035c) ppg12_ tin1 ressel (0 - 32 3, 2 rlt0_u fset - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_31 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 110 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin431 (0x035e) ppg12_ tin2 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin432 (0x0360) ppg12_ tin3 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin433 (0x0362) ppg13_ tin1 ressel (0 - 32 3, 2 rlt0_u fset - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_31 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin434 (0x0364) ppg13_ tin2 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin435 (0x0366) ppg13_ tin3 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 111 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin436 (0x0368) ppg14_ tin1 ressel (0 - 32 3, 2 rlt0_u fset - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_31 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin437 (0x036a) ppg14_ tin2 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin438 (0x036c) ppg14_ tin3 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin439 (0x036e) ppg15_ tin1 ressel (0 - 32 3, 2 rlt0_u fset - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_31 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin440 (0x0370) ppg15_ tin2 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 112 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin441 (0x0372) ppg15_ tin3 ressel (0 - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 113 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin490 (0x03d4) adc12b 0_hwtr g0 ressel (0 - 32 3, / fset / fset 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin491 (0x03d6) adc12b 0_hwtr g1 ressel (0 - 32 3, / fset / 6 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin492 (0x03d8) adc12b 0_hwtr g2 ressel (0 - 32 3, / 6 / 6 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin493 (0x03da) adc12b 0_hwtr g3 ressel (0 - 32 3, / 6 / fset 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin494 (0x03dc) adc12b 0_hwtr g4 ressel (0 - 32 3, / fset / 6 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 114 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin495 (0x03de) adc12b 0_hwtr g5 ressel (0 - 32 3, / fset / 6 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin496 (0x03e0) adc12b 0_hwtr g6 ressel (0 - 32 3, / 6 / fset 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin497 (0x03e2) adc12b 0_hwtr g7 ressel (0 - 32 3, / 6 / fset 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin498 (0x03e4) adc12b 0_hwtr g8 ressel (0 - 32 3, / fset / 6 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin499 (0x03e6) adc12b 0_hwtr g9 ressel (0 - 32 3, / fset / fset 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
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document number: 002- 10635 rev.** page 129 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin570 (0x0474) adc12b 1_hwtr g16 ressel (0 - 32 3, / fset / 6 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin571 (0x0476) adc12b 1_hwtr g17 ressel (0 - 32 3, / fset / 6 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin572 (0x0478) adc12b 1_hwtr g18 ressel (0 - 32 3, / 6 / fset 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin573 (0x047a) adc12b 1_hwtr g19 ressel (0 - 32 3, / 6 / fset 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin574 (0x047c) adc12b 1_hwtr g20 ressel (0 - 32 3, / fset / 6 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 130 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin575 (0x047e) adc12b 1_hwtr g21 ressel (0 - 32 3, / fset / fset 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin576 (0x0480) adc12b 1_hwtr g22 ressel (0 - 32 3, / 6 / fset 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin577 (0x0482) adc12b 1_hwtr g23 ressel (0 - 32 3, / 6 / 6 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin578 (0x0484) adc12b 1_hwtr g24 ressel (0 - 32 3, / fset / fset 2 2 2 2 33 2 33 2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin579 (0x0486) adc12b 1_hwtr g25 ressel (0 - 32 3, / fset / 6 2 2 2 2 33 2 33 2 - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 131 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin580 (0x0488) adc12b 1_hwtr g26 ressel (0 - 32 3, / 6 / 6 2 2 2 2 33 2 33 2 - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin581 (0x048a) adc12b 1_hwtr g27 ressel (0 - 32 3, / 6 / fset 2 2 2 2 33 2 33 2 - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin582 (0x048c) adc12b 1_hwtr g28 ressel (0 - 32 3, / fset / 6 2 2 2 2 33 2 33 2 - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin583 (0x048e) adc12b 1_hwtr g29 ressel (0 - 32 3, / fset / 6 2 2 2 2 33 2 - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin584 (0x0490) adc12b 1_hwtr g30 ressel (0 - 32 3, / 6 / fset 2 2 2 2 33 2 - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 132 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin585 (0x0492) adc12b 1_hwtr g31 ressel (0 - 32 3, / 6 / fset 2 2 2 2 33 2 - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin586 (0x0494) adc12b 1_hwtr g32 ressel (0 - 32 3, / fset / 6 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin587 (0x0496) adc12b 1_hwtr g33 ressel (0 - 32 3, / fset / fset 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin588 (0x0498) adc12b 1_hwtr g34 ressel (0 - 32 3, / 6 / fset 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 133 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin589 (0x049a) adc12b 1_hwtr g35 ressel (0 - 32 3, / 6 / 6 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin590 (0x049c) adc12b 1_hwtr g36 ressel (0 - 32 3, / fset / fset 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin591 (0x049e) adc12b 1_hwtr g37 ressel (0 - 32 3, / fset / 6 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin592 (0x04a0) adc12b 1_hwtr g38 ressel (0 - 32 3, / 6 / 6 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin593 (0x04a2) adc12b 1_hwtr g39 ressel (0 - 32 3, / 6 / fset 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 134 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin594 (0x04a4) adc12b 1_hwtr g40 ressel (0 - 32 3, / fset / 6 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin595 (0x04a6) adc12b 1_hwtr g41 ressel (0 - 32 3, / fset / 6 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin596 (0x04a8) adc12b 1_hwtr g42 ressel (0 - 32 3, / 6 / fset 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin597 (0x04aa) adc12b 1_hwtr g43 ressel (0 - 32 3, / 6 / fset 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin598 (0x04ac) adc12b 1_hwtr g44 ressel (0 - 32 3, / fset / 6 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 135 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin599 (0x04ae) adc12b 1_hwtr g45 ressel (0 - 32 3, / fset / fset 2 2 2 2 - - -- ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin600 (0x04b0) adc12b 1_hwtr g46 ressel (0 - 32 3, / 6 / fset 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin601 (0x04b2) adc12b 1_hwtr g47 ressel (0 - 32 3, / 6 / 6 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin602 (0x04b4) adc12b 1_hwtr g48 ressel (0 - 32 3, / fset / fset 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin603 (0x04b6) adc12b 1_hwtr g49 ressel (0 - 32 3, / fset / 6 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 136 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin604 (0x04b8) adc12b 1_hwtr g50 ressel (0 - 32 3, / 6 / 6 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin605 (0x04ba) adc12b 1_hwtr g51 ressel (0 - 32 3, / 6 / fset 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin606 (0x04bc) adc12b 1_hwtr g52 ressel (0 - 32 3, / fset / 6 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin607 (0x04be) adc12b 1_hwtr g53 ressel (0 - 32 3, / fset / 6 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin608 (0x04c0) adc12b 1_hwtr g54 ressel (0 - 32 3, / 6 / fset 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 137 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin609 (0x04c2) adc12b 1_hwtr g55 ressel (0 - 32 3, / 6 / fset 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin610 (0x04c4) adc12b 1_hwtr g56 ressel (0 - 32 3, / fset / 6 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin611 (0x04c6) adc12b 1_hwtr g57 ressel (0 - 32 3, / fset / fset 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin612 (0x04c8) adc12b 1_hwtr g58 ressel (0 - 32 3, / 6 / fset 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin613 (0x04ca) adc12b 1_hwtr g59 ressel (0 - 32 3, / 6 / 6 2 2 2 2 - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 138 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin614 (0x04cc) adc12b 1_hwtr g60 ressel (0 - 32 3, / fset / fset 2 2 2 2 - - ppg1_t out2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin615 (0x04ce) adc12b 1_hwtr g61 ressel (0 - 32 3, / fset / 6 2 2 2 2 - ppg0_t out0 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin616 (0x04d0) adc12b 1_hwtr g62 ressel (0 - 32 3, / 6 / 6 2 2 2 2 - ppg0_t out2 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin617 (0x04d2) adc12b 1_hwtr g63 ressel (0 - 32 3, / 6 / fset 2 2 2 2 - ppg1_t out0 33 2 66/ -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 139 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin626 (0x04e4) ddrhss pi_ms ta rt ressel (0 - - tot0 tot16 - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin629 (0x04ea) mdio ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_06 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin630 (0x04ec) crs ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p0_20 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin631 (0x04ee) rxd0 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_04 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin632 (0x04f0) rxd1 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p4_06 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 140 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin633 (0x04f2) rxd2 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p4_07 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin634 (0x04f4) rxd3 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_05 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin635 (0x04f6) col ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p0_19 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin636 (0x04f8) rxdv ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p4_02 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin637 (0x04fa) rxer ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p4_01 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 141 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin638 (0x04fc) rxclk ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p4_00 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin639 (0x04fe) txclk ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p4_03 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin643 (0x0506) i2s0_ws ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_26 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin644 (0x0508) i2s0_sd ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_25 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin645 (0x050a) i2s0_sc k ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_27 - - - - - - portse l (8 -15) - - - - - - - -
document number: 002- 10635 rev.** page 142 of 247 s6j33 10/20/30/40 series preliminar register (offset) resource ressel [3:0] /port sel[3:0] source for resource input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ric_re sin646 (0x050c) i2s0_ec lk ressel (0 -7) port_ pin sysc1_ clk_c d4 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p3_24 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin650 (0x0514) i2s1_ec lk ressel (0 -7) port_ pin sysc1_ clk_c d4 - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - - - - - - - - - portse l (8 -15) - - - - - - - - ric_re sin685 (0x055a) adtrg0 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p2_10 - - - - - - portse l (8 -15) - - - - - - - - ric_re sin686 (0x055c) adtrg1 ressel (0 - - - - - - - - - ressel (8 -15) - - - - - - - - portse l (0 - 3 p1_08 p2_11 - - - - - portse (8 -15) - - - - - - - - otes ? when both gpio_porten.gporten and ppc_pcfgr.pie are configured as 0, the input signal is disconnected and external interrupt cannot be detected. during disconnecting, i/o internally outputs "low" to internal logic, and if elvr is configured as low - level - detection, falling - edge- detection, or both - edge- detection it will be detected as external interrupt with eirr=1. ? "set 0" (set 1) means that "0" ("1") is inputted. ? ocux_modn is described as modn pin in traveo tm platform hardware manual .
document number: 002- 10635 rev.** page 143 of 247 s6j33 10/20/30/40 series preliminar 7.2 port output function configuration the port output function configuration (pof) is a function to select a function to output to a port. a resource which supports a port output relocation has its ppc_pcfgr.pof to configure resource output. 2 stanar oniration s633 register (offset) port resource functional outputs pof=0 pof=1 pof=2 pof=3 pof=4 pof=5 pof=6 pof=7 ppc_pcf gr000 (0x0000) p0_00 gpio_po dr0:pod 00 - lcdd5 - - dsp0_r7 _0 - mad1 ppc_pcf gr001 (0x0002) p0_01 gpio_po dr0:pod 01 - lcdd6 arh0_ai c1_dncl k - dsp0_g0 _0 - mad2 ppc_pcf gr002 (0x0004) p0_02 gpio_po dr0:pod 02 6 lcdd7 arh0_ai c1_tda1 arh0_ai c1_dnda ta1 63 scl1 mad3 ppc_pcf gr003 (0x0006) p0_03 gpio_po dr0:pod 03 62 lcdd8 arh0_ai c1_dbg_ out_1 - dsp0_g2 _0 sda1 mad4 ppc_pcf gr004 (0x0008) p0_04 gpio_po dr0:pod 04 66 lcdd9 arh0_ai c1_dbg_ out_0 - dsp0_g3 _0 - mad5 ppc_pcf gr005 (0x000a) p0_05 gpio_po dr0:pod 05 66 lcdd10 arh0_ai c1_tda0 arh0_ai c1_dnda ta0 63 sot0_1 mad6 ppc_pcf gr006 (0x000c) p0_06 gpio_po dr0:pod 06 66 lcdd11 sck0_1 - dsp0_g5 _0 ppg0_to ut0_1 mad7 ppc_pcf gr007 (0x000e) p0_07 gpio_po dr0:pod 07 66 lcdd12 scs00_1 i2s1_sd_ 0 dsp0_g6 _0 ppg0_to ut2_1 mad8 ppc_pcf gr008 (0x0010) p0_08 gpio_po dr0:pod 08 - lcdd13 - i2s1_ws _0 dsp0_g7 _0 ppg1_to ut0_1 mad9 ppc_pcf gr009 (0x0012) p0_09 gpio_po dr0:pod 09 - lcdd14 arh0_ai c0_dncl k ,66 dsp0_b0 _0 ppg1_to ut2_1 mad10 ppc_pcf gr010 (0x0014) p0_10 gpio_po dr0:pod 10 66 lcdd15 arh0_ai c0_tda1 arh0_ai c0_dnda ta1 63 ppg2_to ut0_1 mad11 ppc_pcf gr011 (0x0016) p0_11 gpio_po dr0:pod 11 - lcdd16 arh0_ai c0_dbg_ out_1 ,66 dsp0_b2 _0 ppg2_to ut2_1 mad12 ppc_pcf gr012 (0x0018) p0_12 gpio_po dr0:pod 12 - lcdd17 arh0_ai c0_dbg_ out_0 i2s0_ws _0 dsp0_b3 _0 ppg3_to ut0_1 mad13 ppc_pcf gr013 (0x001a) p0_13 gpio_po dr0:pod 13 - cs# - i2s0_sc k_0 dsp0_b4 _0 ppg3_to ut2_1 mad14
document number: 002- 10635 rev.** page 144 of 247 s6j33 10/20/30/40 series preliminar register (offset) port resource functional outputs pof=0 pof=1 pof=2 pof=3 pof=4 pof=5 pof=6 pof=7 ppc_pcf gr014 (0x001c) p0_14 gpio_po dr0:pod 14 - wr# - - dsp0_b5 _0 sck4_1 moex ppc_pcf gr015 (0x001e) p0_15 gpio_po dr0:pod 15 - rd# - - dsp0_b6 _0 scs40_1 mwex ppc_pcf gr016 (0x0020) p0_16 gpio_po dr0:pod 16 dsp0_b7 _1 - arh0_ai c0_tda0 arh0_ai c0_dnda ta0 - scs41_1 mclk ppc_pcf gr017 (0x0022) p0_17 gpio_po dr0:pod 17 - - - - dsp0_b7 _0 scs43_1 mdqm0 ppc_pcf gr018 (0x0024) p0_18 gpio_po dr0:pod 18 - rs - mdc_1 - - mcsx2 ppc_pcf gr019 (0x0026) p0_19 gpio_po dr0:pod 19 - res# - - - - mcsx3 ppc_pcf gr020 (0x0028) p0_20 gpio_po dr0:pod 20 - - - - - - - ppc_pcf gr021 (0x002a) p0_21 gpio_po dr0:pod 21 - m_sd ata 0_0 txen_0 m_dq3 - - - ppc_pcf gr022 (0x002c) p0_22 gpio_po dr0:pod 22 sck2_0 m_sd ata 0_2 txd0_0 m_dq2 sot9_2 - - ppc_pcf gr023 (0x002e) p0_23 gpio_po dr0:pod 23 62 m_sd ata 0_1 txd1_0 m_dq1 sck9_2 - - ppc_pcf gr024 (0x0030) p0_24 gpio_po dr0:pod 24 scs20_0 m_ssel0 txd2_0 m_dq0 scs90_2 - - ppc_pcf gr025 (0x0032) p0_25 gpio_po dr0:pod 25 66 m_sd ata 0_3 txd3_0 m_cs#_1 scs91_2 - - ppc_pcf gr026 (0x0034) p0_26 gpio_po dr0:pod 26 scs22_0 m_sclk0 txer_0 m_ck - - - ppc_pcf gr027 (0x0036) p0_27 gpio_po dr0:pod 27 66 m_sd ata 1_0 - m_rwds - - - ppc_pcf gr028 (0x0038) p0_28 gpio_po dr0:pod 28 - m_sd ata 1_2 - m_dq4 sck8_2 - -
document number: 002- 10635 rev.** page 145 of 247 s6j33 10/20/30/40 series preliminar register (offset) port resource functional outputs pof=0 pof=1 pof=2 pof=3 pof=4 pof=5 pof=6 pof=7 ppc_pcf gr029 (0x003a) p0_29 gpio_po dr0:pod 29 sck3_0 m_sd ata 1_1 - m_dq5 sot8_2 - - ppc_pcf gr030 (0x003c) p0_30 gpio_po dr0:pod 30 62 m_ssel1 - m_dq6 scs80_2 - - ppc_pcf gr031 (0x003e) p0_31 gpio_po dr0:pod 31 scs30_0 m_sd ata 1_3 mdio_0 m_dq7 - - - ppc_pcf gr100 (0x0040) p1_00 gpio_po dr1:pod 00 66 - mdc_0 m_cs#_2 - - - ppc_pcf gr101 (0x0042) p1_01 gpio_po dr1:pod 01 scs32_0 - - - - - mlbsig ppc_pcf gr102 (0x0044) p1_02 gpio_po dr1:pod 02 66 - - - - - mlbdat ppc_pcf gr103 (0x0046) p1_03 gpio_po dr1:pod 03 - - - ocu0_o td0_0 - ppg0_to ut0_0 bn0(bl0) ppc_pcf gr104 (0x0048) p1_04 gpio_po dr1:pod 04 6 - scl0 ocu0_o td1_0 tot0_0 ppg0_to ut2_0 bp0(bh0) ppc_pcf gr105 (0x004a) p1_05 gpio_po dr1:pod 05 sot0_0 sga0_0 sda0 trace0_ 0 - ppg1_to ut0_0 an0(al0) ppc_pcf gr106 (0x004c) p1_06 gpio_po dr1:pod 06 66 sgo0_0 tx0_0 trace1_ 0 tot1_0 ppg1_to ut2_0 ap0(ah0) ppc_pcf gr107 (0x004e) p1_07 gpio_po dr1:pod 07 - sga1_0 trace2_ 0 ocu1_o td0_0 - ppg2_to ut0_0 bn1(bl1) ppc_pcf gr108 (0x0050) p1_08 gpio_po dr1:pod 08 sgo1_0 tx1_0 ocu1_o td1_0 tot16_0 ppg2_to ut2_0 bp1(bh1) ppc_pcf gr109 (0x0052) p1_09 gpio_po dr1:pod 09 sck16_0 sga2_0 scl16 ocu2_o td0_0 trace_ ctl_0 ppg3_to ut0_0 an1(al1) ppc_pcf gr110 (0x0054) p1_10 gpio_po dr1:pod 10 62 sgo2_0 sda16 ocu2_o td1_0 trace_ clk_0 ppg3_to ut2_0 ap1(ah1) ppc_pcf gr111 (0x0056) p1_11 gpio_po dr1:pod 11 scs160_ 0 indicat or0_0 - ocu8_o td0_0 - ppg4_to ut0_0 -
document number: 002- 10635 rev.** page 146 of 247 s6j33 10/20/30/40 series preliminar register (offset) port resource functional outputs pof=0 pof=1 pof=2 pof=3 pof=4 pof=5 pof=6 pof=7 ppc_pcf gr112 (0x0058) p1_12 gpio_po dr1:pod 12 scs161_ 0 - - ocu8_o td1_0 tot17_0 ppg4_to ut2_0 tx2_0 ppc_pcf gr113 (0x005a) p1_13 gpio_po dr1:pod 13 - sga3_0 - ocu9_o td0_0 - - - ppc_pcf gr114 (0x005c) p1_14 gpio_po dr1:pod 14 sysc0_c lk_1 sgo3_0 - ocu9_o td1_0 tot48_0 ppg5_to ut0_0 tx3_0 ppc_pcf gr115 (0x005e) p1_15 gpio_po dr1:pod 15 6 sga4_0 scl17 ocu10_ otd0_0 sck12_1 ppg5_to ut2_0 indicat or0_1 ppc_pcf gr116 (0x0060) p1_16 gpio_po dr1:pod 16 sot17_0 sgo4_0 sda17 ocu10_ otd1_0 tot49_0 sysc0_c lk_0 wot ppc_pcf gr117 (0x0062) p1_17 gpio_po dr1:pod 17 66 - - - pwm1p0 ppg6_to ut0_0 - ppc_pcf gr118 (0x0064) p1_18 gpio_po dr1:pod 18 scs171_ 0 - - - pwm1m0 ppg6_to ut2_0 tx5_0 ppc_pcf gr119 (0x0066) p1_19 gpio_po dr1:pod 19 - - - - pwm2p0 ppg7_to ut0_0 - ppc_pcf gr120 (0x0068) p1_20 gpio_po dr1:pod 20 sck8_0 - scl8 - pwm2m0 ppg7_to ut2_0 - ppc_pcf gr121 (0x006a) p1_21 gpio_po dr1:pod 21 62 - sda8 - pwm1p1 ppg8_to ut0_0 - ppc_pcf gr122 (0x006c) p1_22 gpio_po dr1:pod 22 scs80_0 - - - pwm1m1 ppg8_to ut2_0 tx6_0 ppc_pcf gr123 (0x006e) p1_23 gpio_po dr1:pod 23 - - - - pwm2p1 ppg9_to ut0_0 - ppc_pcf gr124 (0x0070) p1_24 gpio_po dr1:pod 24 sck9_0 - scl9 - pwm2m1 ppg9_to ut2_0 - ppc_pcf gr125 (0x0072) p1_25 gpio_po dr1:pod 25 62 - sda9 - pwm1p2 ppg10_t out0_0 - ppc_pcf gr126 (0x0074) p1_26 gpio_po dr1:pod 26 scs90_0 - - - pwm1m2 ppg10_t out2_0 -
document number: 002- 10635 rev.** page 147 of 247 s6j33 10/20/30/40 series preliminar register (offset) port resource functional outputs pof=0 pof=1 pof=2 pof=3 pof=4 pof=5 pof=6 pof=7 ppc_pcf gr127 (0x0076) p1_27 gpio_po dr1:pod 27 scs91_0 - - - pwm2p2 ppg11_t out0_0 - ppc_pcf gr128 (0x0078) p1_28 gpio_po dr1:pod 28 - - - - pwm2m2 ppg11_t out2_0 - ppc_pcf gr129 (0x007a) p1_29 gpio_po dr1:pod 29 sck10_0 - scl10 - pwm1p3 - - ppc_pcf gr130 (0x007c) p1_30 gpio_po dr1:pod 30 62 - sda10 - pwm1m3 ppg12_t out0_0 - ppc_pcf gr131 (0x007e) p1_31 gpio_po dr1:pod 31 scs100_ 0 - - - pwm2p3 ppg12_t out2_0 - ppc_pcf gr200 (0x0080) p2_00 gpio_po dr2:pod 00 - - - - pwm2m3 ppg13_t out0_0 - ppc_pcf gr201 (0x0082) p2_01 gpio_po dr2:pod 01 sck11_0 - scl11 - pwm1p4 ppg13_t out2_0 - ppc_pcf gr202 (0x0084) p2_02 gpio_po dr2:pod 02 62 - sda11 - pwm1m4 ppg14_t out0_0 - ppc_pcf gr203 (0x0086) p2_03 gpio_po dr2:pod 03 scs110_ 0 - - - pwm2p4 ppg14_t out2_0 - ppc_pcf gr204 (0x0088) p2_04 gpio_po dr2:pod 04 66 - - - pwm2m4 ppg15_t out0_0 - ppc_pcf gr205 (0x008a) p2_05 gpio_po dr2:pod 05 - - - - pwm1p5 ppg15_t out2_0 - ppc_pcf gr206 (0x008c) p2_06 gpio_po dr2:pod 06 6 - scl12 - pwm1m5 - - ppc_pcf gr207 (0x008e) p2_07 gpio_po dr2:pod 07 sot12_0 - sda12 - pwm2p5 - - ppc_pcf gr208 (0x0090) p2_08 gpio_po dr2:pod 08 66 - - - pwm2m5 - - ppc_pcf gr209 (0x0092) p2_09 gpio_po dr2:pod 09 scs23_1 - - - dsp0_en _0 ppg14_t out0_1 mcsx0
document number: 002- 10635 rev.** page 148 of 247 s6j33 10/20/30/40 series preliminar register (offset) port resource functional outputs pof=0 pof=1 pof=2 pof=3 pof=4 pof=5 pof=6 pof=7 ppc_pcf gr210 (0x0094) p2_10 gpio_po dr2:pod 10 scs31_1 - - - dsp0_hs ync_0 - mcsx1 ppc_pcf gr211 (0x0096) p2_11 gpio_po dr2:pod 11 66 - - - dsp0_vs ync_0 - mdata0 ppc_pcf gr212 (0x0098) p2_12 gpio_po dr2:pod 12 scs33_1 - - - dsp0_cl k_0 - mdata1 ppc_pcf gr213 (0x009a) p2_13 gpio_po dr2:pod 13 - - - - dsp0_r0 _0 - mdata2 ppc_pcf gr214 (0x009c) p2_14 gpio_po dr2:pod 14 sck4_0 - scl4 - dsp0_r1 _0 - mdata3 ppc_pcf gr215 (0x009e) p2_15 gpio_po dr2:pod 15 62 lcdd0 sda4 - dsp0_r2 _0 - mdata4 ppc_pcf gr216 (0x00a0) p2_16 gpio_po dr2:pod 16 scs40_0 lcdd1 - - dsp0_r3 _0 - mdata5 ppc_pcf gr217 (0x00a2) p2_17 gpio_po dr2:pod 17 66 lcdd2 - - dsp0_r4 _0 - mdata6 ppc_pcf gr218 (0x00a4) p2_18 gpio_po dr2:pod 18 scs42_0 lcdd3 - - dsp0_r5 _0 - mdata7 ppc_pcf gr219 (0x00a6) p2_19 gpio_po dr2:pod 19 66 lcdd4 - - dsp0_r6 _0 - mad0 ppc_pcf gr300 (0x00c0) p3_00 gpio_po dr3:pod 00 - txd1_1 - - - ppg4_to ut0_1 mad15 ppc_pcf gr301 (0x00c2) p3_01 gpio_po dr3:pod 01 6 txd2_1 - - - ppg4_to ut2_1 mad16 ppc_pcf gr302 (0x00c4) p3_02 gpio_po dr3:pod 02 sot1_1 txd3_1 - - - ppg5_to ut0_1 mad17 ppc_pcf gr303 (0x00c6) p3_03 gpio_po dr3:pod 03 66 txer_1 - - - ppg5_to ut2_1 mad18 ppc_pcf gr304 (0x00c8) p3_04 gpio_po dr3:pod 04 scs11_1 - - - - - mad19
document number: 002- 10635 rev.** page 149 of 247 s6j33 10/20/30/40 series preliminar register (offset) port resource functional outputs pof=0 pof=1 pof=2 pof=3 pof=4 pof=5 pof=6 pof=7 ppc_pcf gr305 (0x00ca) p3_05 gpio_po dr3:pod 05 scs12_1 - - - - - mad20 ppc_pcf gr306 (0x00cc) p3_06 gpio_po dr3:pod 06 66 mdio_1 - - - sot4_1 mad21 ppc_pcf gr307 (0x00ce) p3_07 gpio_po dr3:pod 07 - - - - - scs42_1 mdqm1 ppc_pcf gr308 (0x00d0) p3_08 gpio_po dr3:pod 08 - sga0_1 ppg6_to ut0_1 ocu0_o td0_1 - - - ppc_pcf gr309 (0x00d2) p3_09 gpio_po dr3:pod 09 sck8_1 sgo0_1 ppg6_to ut2_1 ocu0_o td1_1 tot0_1 - - ppc_pcf gr310 (0x00d4) p3_10 gpio_po dr3:pod 10 62 sga1_1 ppg7_to ut0_1 ocu1_o td0_1 trace0_ 1 - tx0_1 ppc_pcf gr311 (0x00d6) p3_11 gpio_po dr3:pod 11 scs80_1 sgo1_1 ppg7_to ut2_1 ocu1_o td1_1 tot1_1 trace1_ 1 - ppc_pcf gr312 (0x00d8) p3_12 gpio_po dr3:pod 12 - sga2_1 ppg8_to ut0_1 ocu2_o td0_1 - trace2_ 1 tx1_1 ppc_pcf gr313 (0x00da) p3_13 gpio_po dr3:pod 13 sck10_1 sgo2_1 ppg8_to ut2_1 ocu2_o td1_1 tot16_1 trace3_ 1 - ppc_pcf gr314 (0x00dc) p3_14 gpio_po dr3:pod 14 62 sga3_1 ppg9_to ut0_1 ocu8_o td0_1 - trace_ ctl_1 - ppc_pcf gr315 (0x00de) p3_15 gpio_po dr3:pod 15 scs100_ 1 sgo3_1 ppg9_to ut2_1 ocu8_o td1_1 tot17_1 trace_ clk_1 tx2_1 ppc_pcf gr316 (0x00e0) p3_16 gpio_po dr3:pod 16 - sga4_1 ppg10_t out0_1 ocu9_o td0_1 - - - ppc_pcf gr317 (0x00e2) p3_17 gpio_po dr3:pod 17 - sgo4_1 ppg10_t out2_1 ocu9_o td1_1 tot48_1 - tx3_1 ppc_pcf gr318 (0x00e4) p3_18 gpio_po dr3:pod 18 - - ppg11_t out0_1 ocu10_ otd0_1 - - - ppc_pcf gr319 (0x00e6) p3_19 gpio_po dr3:pod 19 sck9_1 - ppg11_t out2_1 ocu10_ otd1_1 - - -
document number: 002- 10635 rev.** page 150 of 247 s6j33 10/20/30/40 series preliminar register (offset) port resource functional outputs pof=0 pof=1 pof=2 pof=3 pof=4 pof=5 pof=6 pof=7 ppc_pcf gr320 (0x00e8) p3_20 gpio_po dr3:pod 20 sot9_1 - - - - - tx5_1 ppc_pcf gr321 (0x00ea) p3_21 gpio_po dr3:pod 21 66 - - - tot49_1 - - ppc_pcf gr322 (0x00ec) p3_22 gpio_po dr3:pod 22 scs91_1 - - - - - - ppc_pcf gr323 (0x00ee) p3_23 gpio_po dr3:pod 23 - - - - scs120_ 1 - tx6_1 ppc_pcf gr324 (0x00f0) p3_24 gpio_po dr3:pod 24 sot2_1 - - - - ppg12_t out0_1 mdata8 ppc_pcf gr325 (0x00f2) p3_25 gpio_po dr3:pod 25 66 - - - i2s0_sd_ 1 ppg12_t out2_1 mdata9 ppc_pcf gr326 (0x00f4) p3_26 gpio_po dr3:pod 26 scs21_1 - - - i2s0_ws _1 ppg13_t out0_1 mdata10 ppc_pcf gr327 (0x00f6) p3_27 gpio_po dr3:pod 27 66 - - - i2s0_sc k_1 ppg13_t out2_1 mdata 11 ppc_pcf gr328 (0x00f8) p3_28 gpio_po dr3:pod 28 - - - - - ppg14_t out2_1 mdata12 ppc_pcf gr329 (0x00fa) p3_29 gpio_po dr3:pod 29 6 - - - - ppg15_t out0_1 mdata13 ppc_pcf gr330 (0x00fc) p3_30 gpio_po dr3:pod 30 sot3_1 - - - - ppg15_t out2_1 mdata14 ppc_pcf gr331 (0x00fe) p3_31 gpio_po dr3:pod 31 66 - - - - - mdata15 ppc_pcf gr400 (0x0100) p4_00 gpio_po dr4:pod 00 - - - - - - - ppc_pcf gr401 (0x0102) p4_01 gpio_po dr4:pod 01 - - - - tx0_2 - - ppc_pcf gr402 (0x0104) p4_02 gpio_po dr4:pod 02 - - - - - - -
document number: 002- 10635 rev.** page 151 of 247 s6j33 10/20/30/40 series preliminar register (offset) port resource functional outputs pof=0 pof=1 pof=2 pof=3 pof=4 pof=5 pof=6 pof=7 ppc_pcf gr403 (0x0106) p4_03 gpio_po dr4:pod 03 - - scs170_ 1 - - - - ppc_pcf gr404 (0x0108) p4_04 gpio_po dr4:pod 04 - txen_1 sck17_1 - tx3_2 - - ppc_pcf gr405 (0x010a) p4_05 gpio_po dr4:pod 05 - txd0_1 sot17_1 - - - - ppc_pcf gr406 (0x010c) p4_06 gpio_po dr4:pod 06 - - - - - - - ppc_pcf gr407 (0x010e) p4_07 gpio_po dr4:pod 07 - - - - - - - ppc_pcf gr408 (0x0110) p4_08 gpio_po dr4:pod 08 - - - - - - - ppc_pcf gr409 (0x0112) p4_09 gpio_po dr4:pod 09 - - - - - - - ppc_pcf gr410 (0x0114) p4_10 gpio_po dr4:pod 10 - - - - - - - ppc_pcf gr411 (0x0116) p4_11 gpio_po dr4:pod 11 - - - - - - - ppc_pcf gr412 (0x0118) p4_12 gpio_po dr4:pod 12 - - - - - - - ppc_pcf gr413 (0x011a) p4_13 gpio_po dr4:pod 13 - - - - - - - ppc_pcf gr414 (0x011c) p4_14 gpio_po dr4:pod 14 - - - - - - - ppc_pcf gr415 (0x011e) p4_15 gpio_po dr4:pod 15 - - - - - - - ppc_pcf gr416 (0x0120) p4_16 gpio_po dr4:pod 16 - - - - - - - ppc_pcf gr417 (0x0122) p4_17 gpio_po dr4:pod 17 - - - - sot12_1 - -
document number: 002- 10635 rev.** page 152 of 247 s6j33 10/20/30/40 series preliminar register (offset) port resource functional outputs pof=0 pof=1 pof=2 pof=3 pof=4 pof=5 pof=6 pof=7 ppc_pcf gr418 (0x0124) p4_18 gpio_po dr4:pod 18 - - - - - - - ppc_pcf gr419 (0x0126) p4_19 gpio_po dr4:pod 19 - - - - - - - ppc_pcf gr420 (0x0128) p4_20 gpio_po dr4:pod 20 - - - - sot16_1 - - ppc_pcf gr421 (0x012a) p4_21 gpio_po dr4:pod 21 - - - - sck16_1 - - ppc_pcf gr422 (0x012c) p4_22 gpio_po dr4:pod 22 - - - - scs161_ 1 - - ppc_pcf gr423 (0x012e) p4_23 gpio_po dr4:pod 23 - - - - scs160_ 1 - - ppc_pcf gr424 (0x0130) p4_24 gpio_po dr4:pod 24 - - - - - - - ppc_pcf gr425 (0x0132) p4_25 gpio_po dr4:pod 25 - - - - - - - ppc_pcf gr426 (0x0134) p4_26 gpio_po dr4:pod 26 - - - - - - - ppc_pcf gr427 (0x0136) p4_27 gpio_po dr4:pod 27 - - - - - - - ppc_pcf gr428 (0x0138) p4_28 gpio_po dr4:pod 28 - - - - - - - ppc_pcf gr429 (0x013a) p4_29 gpio_po dr4:pod 29 - - - - - - - ppc_pcf gr430 (0x013c) p4_30 gpio_po dr4:pod 30 - - - - - - - ppc_pcf gr431 (0x013e) p4_31 gpio_po dr4:pod 31 6 - - - - - -
document number: 002- 10635 rev.** page 153 of 247 s6j33 10/20/30/40 series preliminar notes: ? the hyphen indicates that setting is prohibited. if setting the port will be operated as input independent on the register va lue of the gpio_ddr. ? the register for p0_20 for pof exists though the port only supports input not supports output. the configuration of pof=0 for the port doesnt affect anything.
document number: 002- 10635 rev.** page 154 of 247 s6j33 10/20/30/40 series preliminar 8. precautions and handling devices 8.1 handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the co nditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your cypress semiconductor devices. recations or roct desin this section describes precautions when designing electronic equipment using semiconductor devices. absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. recommended operating co nditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operati ng conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering applicat ion outside the listed conditions are advised to contact their sales representative beforehand. processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/outpu t functions. (1) preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the dev ice, and in extreme cases leads to permanent damage of the devi ce. try to prevent such overvoltage or over - current conditions at the design stage. (2) protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows . such condition s if present for extended periods of time can damage the device. therefore, avoid this type of connection. (3) handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins shoul d be connected through an appropriate resistance to a power supply pin or ground pin.
document number: 002- 10635 rev.** page 155 of 247 s6j33 10/20/30/40 series preliminar 8.1.2 precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during solderin g, you sho uld only mount under cypress s recommended conditions. for detailed information about mount conditions, contact your sales representative. lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. in thi s case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic lead s be verified before mounting. sur face mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advi sed to mount packages in accordance with cypress ranking of recommended conditions. lead - free packaging caution: when ball grid array (bga) packages with sn -ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be reduced under some conditions of use. storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorpt ion of moisture. during mounting, the application of heat to a package that ha s absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: (1) avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products i n locations where temperature changes are slight. (2) use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 ? c and 30 ?c. when you open dry package that recommends humidity 40% to 70% relati ve humidity. (3) when necessary, cypress packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. (4) avoid storing packages where they are exposed to corrosive gases or high levels of dust. baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the cypress recommended conditions for baking. condition: 125 ?c/24 h static electricity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. (2) electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the le vel of 1 m ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) ground all fixtures and instruments, or protect with anti - static measures. (5) avoid the use of styrofoam or other hig hly static - prone materials for storage of completed board assemblies.
document number: 002- 10635 rev.** page 156 of 247 s6j33 10/20/30/40 series preliminar 8.1.3 precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: (1) humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. (2) discharge of static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. (3) corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chem ical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) radiation, including cosmic radiation most devices are not designed for environments involvin g exposure to radiation or cosmic radiation. users should provide shielding as appropriate. (5) smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, the re is danger of the release of toxic gases. customers considering the use of cypress products in other special environmental conditions should consult with sales representatives.
document number: 002- 10635 rev.** page 157 of 247 s6j33 10/20/30/40 series preliminar 8.2 handling devices for latch - up prevention the latch - up phenomenon may occu r on a cmos ic in the following cases: the voltage applied to an input or output pin is higher than vcc or lower than vss; or the voltage applied between a vcc pin and a vss pin exceeds the rating. a latch - up causes a rapid increase in the power supply cur rent, possibly resulting in thermal damage to an element. when using the device, take sufficient care not to exceed the maximum rating. also be careful that analog power supplies (avcc5,avrh5) and analog inputs do not exceed the digital power supply (vcc) at the analog system power - on and power - off times. the power - on sequence is as follows. simultaneously turn on the digital supply voltage (vcc) and analog supply voltages (avcc5,avrh5), or turn on the digital supply voltage (vcc) and then the analog supp ly voltages (avcc5,avrh5). about handling unused pins leaving unused input pins open may cause permanent damage from a malfunction or latch - up. take measures for unused pins, such as pulling up or pulling down the voltage with resistors of 2 kilo ohms or h igher. if there are any unused input/output pins, set them to the output state and then open them, or set them to the input state an d handle them in the same way as input pins. about power supply pins if the device has multiple vcc and vss pins, the devic e is designed in such a way that the pins that should be at the same potential are connected to each other inside the device to prevent malfunctions such as latch - up. however, to reduce unwanted emissions, prevent malfunctions of strobe signals caused by a n increase of the ground level, and observe standards on total output current, be sure to connect all the vcc and vss pins to the power source and ground externally. also handle all the vs s power supply pins in this way as shown in the following diagram. i f there are multiple vcc or vss systems, the device does not operate normally even within the guaranteed operating range. figure 8 - 1 pin assignment in addition, consider connecting with low impedance from the power supply source to the vcc and vss of this device. we recommend connecting a ceramic capacitor as a bypass capacitor between vcc and vss, near this device. about the crystal oscillation circuit noise entering the x0 or x1 pin may cause a malfunction. design the printed circuit board in such a way that the x0 and x1 pi ns, the crystal oscillator (or ceramic resonator), and a bypass capacitor to ground are located very close to the device. we recom mend that the printed circuit board artwork have the x0 and x1 pins enclosed by ground.
document number: 002- 10635 rev.** page 158 of 247 s6j33 10/20/30/40 series preliminar about the mode pin (mode) use mode pin mode by directly connecting it to a vcc or vss pin. to prevent noise from causing the device to accidentally enter test mode, reduce the pattern length between each mode pin and a vcc or vss pin on the printed circuit board, and connect them with low impedance. about the power - on time to prevent the internal built - in voltage step- down circuit from malfunctioning, secure a voltage rising time of 50 s (between 0.2 v and 2.7 v) or longer at the power - on time. point to note during pll clock operation while a pll clock is selected, if the oscillator breaks off or input stops, the pll clock may continue operating with the fre e running frequency of the internal self - oscillator circuit. this operation is outside of the guaranteed range. power supply pin processing of an a/d converter even when no a/d converter is used, establish a connection such that avcc5=avrh5=vcc5 and avss/avrl5=vss. points to note about using external clocks external clocks are not supported. external direct clock input cannot be used. power - on sequence of the power supply analog inputs of an a/d converter be sure to turn on the digital power supply (vcc) before the application of the power supplies (avcc, avrh, and avrl) and analog inputs (an0 to an63) of an a/d converter. at the power - off time, turn off the power supplies and analog inputs of the a/d converter, and then turn off the digital power supply (vcc). per form these power - on and power - off operations without avrh exceeding avcc. even when using a pin shared with an analog input as an input port, do not allow the input voltage to exceed avcc. (turning on or off the analog supply vo ltage and digital supply vol tage simultaneously is not a problem.) about c pin processing this device has a built - in voltage step - down circuit. be sure to connect a capacitor to the c pin for internal stabilization of the device. for the standard values, see "recommended operating co nditions" in the latest data sheet. precautions on designing a mounting substrate measures against heat generation from the package must be taken for the mounting substrate to observe the absolute maximum rating (operating temperature). design a mounting substrate with 4 or more layers. connect the back of the package stage and the substrate pad with solder paste. arrange thermal via holes on the substrate pad. notes on writing to a register containing a status flag in writing to a register containing a st atus flag (particularly an interrupt request flag, etc.) to control a function, it is important to take care not to accidentally clear the status flag. therefore, before the write operation, configure the status bit such that the flag is not cleared, and then set the control bit to the desired value. especially for control bits configured as a set of multiple bits, bit instructions cannot be used (bit instructions have only 1 - bit access). in such cases, byte, half - word, or word access is used to write to the control bits and a status flag simultaneously. however, at this time, be careful not to accidentally clear bits other than the intended ones (the status flag bit in this ca se). note: bit instructions take this point into account for registers that supp ort bit - band units, so it does not need to be a concern. you need to take care when using bit instructions for registers that do not support bit - band units.
document number: 002- 10635 rev.** page 159 of 247 s6j33 10/20/30/40 series preliminar 9. electric characteristics 9.1 electrical characteristics this chapter contains target values and information. target values and information are subjects to change without notice. bsolte maimm atin parameter symbol rating unit remarks min max power supply voltage *1 , *2 v cc 5 v 0.3 v +6.0 v v cc 53 v 0.3 v +6.0 v v cc 53 v cc 5 v cc v 0.3 v +4.0 v v cc v cc 5 dv cc v 0.3 v +6.0 v dv cc v cc 5 v cc 12 v ss - 0.3 v ss +1.8 v v cc 12 v cc 53 3 v cc 12 dv cc v cc 12 av cc 5 analog supply voltage *1 , *2 av cc 5 v 0.3 v +6.0 v av cc 5 v cc 5 avcc3_da c v ss - 0.3 v ss +4.0 v for dac analog reference voltage *1 avrh v 0.3 v +6.0 v avrhav cc 5 input voltage *1 v i1 v 0.3 v cc 5 +0.3 v 5v pins not shared smc v i2 v 0.3 dv cc +0.3 v 5v pins shared smc v i3 v 0.3 v cc +0.3 v 3v pins v ie v 0.3 v cc 5 +0.3 v 5v/3v pins analog pin input voltage *1 v ia v 0.3 v cc 5 +0.3 v output voltage *1 v o1 v 0.3 v cc 5 +0.3 v 5v pins not shared smc v o2 v 0.3 dv cc +0.3 v 5v pins shared smc v o3 v 0.3 v cc +0.3 v 3v pins v o4 v 0.3 v cc 53 +0.3 v 5v/3v pins maximum clamp current |i clamp 4 ma *a total maximum clamp current |i clamp 20 ma *a total maximum clamp current |i clamp 50 ma special spec *a "l" - level maximum output current *3 i ol1 3.5 ma when setting is 1 ma *6, *7, *8 i ol2 7 ma when setting is 2 ma *6, *7, *8, *9 i ol3 10 ma when setting is 5 ma *9 i ol4 16 ma when setting is 10 ma *9 i ol6 40 ma when setting is 30ma *7 i ol7 8 ma when setting is 3ma *10 i ol8 11 ma when setting is 6ma *11 i ol9 21 ma when setting is 15ma *12 "l" - level average output current *4 i olav1 1 ma when setting is 1 ma *6, *7, *8 i olav2 ma when setting is 2 ma *6, *7, *8, *9 i olav3 5 ma when setting is 5 ma *9 i olav4 10 ma when setting is 10 ma *9 i olav6 30 ma when setting is 30ma *7 i olav7 ma when setting is 3ma *10 i olav8 ma when setting is 6ma *11 i olav9 15 ma when setting is 15ma *12 "l" - level total output current *5 i ol1 50 ma *6, *10 i ol2 250 ma *7
document number: 002- 10635 rev.** page 160 of 247 s6j33 10/20/30/40 series preliminar parameter symbol rating unit remarks min max "l" - level total output current *5 i ol3 - , 2/ - 50 ma *9, *11 "h" - level maximum output current *3 i oh1 - - 3.5 ma when setting is 1 ma *6, *7, *8 i oh2 - -7 ma when setting is 2 ma *6, *7, *8, *9 i oh3 - -10 ma when setting is 5 ma *9 i oh4 - -16 ma when setting is 10 ma *9 i oh6 - -40 ma when setting is 30ma *7 i oh8 - -11 ma when setting is 6ma *11 i oh9 21 ma when setting is 15ma *12 "h" - level average output current *4 i ohav1 - -1 ma when setting is 1 ma *6, *7, *8 i ohav2 - -2 ma when setting is 2 ma *6, *7, *8, *9 i ohav3 - -5 ma when setting is 5 ma *9 i ohav4 - -10 ma when setting is 10 ma *9 i ohav6 - -30 ma when setting is 30ma *7 i ohav8 ma when setting is 6ma *11 i ohav9 - -15 ma when setting is 15ma *12 "h" - level total output current *5 i oh1 - -50 ma *6, *10 i oh2 250 ma *7 i oh3 - -50 ma *8 i oh4 50 ma *9 *11 power consumption p 1500 mw operating temperature t a - 40 +105 c p 2000mw 40 +125 c p 1200mw storage temperature ts t g 55 +150 c *1 these parameters are based on the condition that v ss =av ss =dv ss =0.0 v. *2 take care that dv cc , av cc 5 do not exceed v cc 5 at, for example, the power - on time. *3 the maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *4 the average output curr ent is defined as the value of the average current flowing through any one of the corresponding pins for a 10 ms period. the average value is the operation current the operation ratio. *5 the total output current is defined as the maximum current value f lowing through all of corresponding pins. *6 output of 5v pins. *7 output of smc pins. *8 output of 5v/3v pins. *9 output of 3v pins. *10 output of i2c. *11 output of media lb pins *12 output of dsp0_clk pins
document number: 002- 10635 rev.** page 161 of 247 s6j33 10/20/30/40 series preliminar *a relevant pins: all general - purpose ports and analog input pins ? corresponding pins : all general - purpose ports ? use within recommended operating conditions. ? use at dc voltage (current). ? the +b signal should always be applied by connecting a limiting resistor between the +b signal and the microcontr oller. ? the value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated v alues at any time regardless of instantaneously or constantly when the +b signal is input. ? note that when the microcontrolle r drive current is low, such as in the low power consumption modes, the + b input potential can increase the potential at the vcc pin via a protective diode, possibly affecting other devices. ? note that if the + b signal is input when the microcontroller is off (not fixed at 0 v), since the power is supplied through the pin, the microcontroller may operate incompletely. ? note that if the +b signal is input at power - on, since the power is supplied through the pin, the power - on reset may not function in the pow er supply voltage. ? do not leave + b input pins open. example of a recommended circuit ote ? application of stress (e.g., voltage, current, temperature) exceeding the absolute maximum rating may cause damage to the semiconductor device. therefore, make sure that nothing exceeds the rating. S6J3310/20/30/40 series
document number: 002- 10635 rev.** page 162 of 247 s6j33 10/20/30/40 series preliminar 9.1.2 recommended operating condition parameter symbol pin name rating unit remarks min max supply voltage recommended operation assurance range *4 v cc 5 vcc5 4.5 5.5 v *1 3.6 *2 *3 v cc 53 vcc53 4.5 5.5 v *1 3.6 v dv cc dvcc 4.5 5.5 v *1 * 3.0 3.6 * av cc 5 avcc5 4.5 5.5 v *1 3.6 *2 *3 v cc vcc3 3.6 v v cc 12 vcc12 1.09 1.21 v av cc 3_dac 3 6ssyd operation assurance range v cc 5 vcc5 3.5 5.5 v *1 2.6 3.6 *2 *3 v cc 53 vcc53 2.7 5.5 v *1 2.7 3.6 dv cc dvcc 3.5 5.5 v *1 * 2.7 3.6 * av cc 5 avcc5 3.5 5.5 v *1 2.7 3.6 *2 *3 v cc 3 6lqfdsdfl cs c 4.7 f tolerance of up to 40% operating temperature ta 40 105 c pd2000mw ta 40 125 c pd1200mw *1:for s6j33xxxs b or s6j33xxxu b or s6j33xxx tb or s6j33xxx vb option. *2:for s6j33xxxb b or s6j33xxxd b or s6j33xxx fb or s6j33xxx hb option. *3:for s6j33xxxa b or s6j33xxxc b or s6j33xxx eb or s6j33xxx gb option. *4: corresponding functions for low voltage monitoring of supply voltage are described in chapter 13 low voltage detection of s6j3300 series hardware manual. the detection/release threshold values of following lvd channels are potentially below supply range define d in 9.1.2 recommended operating condition (refer to " 9.1.4.11 low voltage detection (external voltage) and 9.1.4.12 low voltage detection (internal voltage) " for detection/release threshold values for these lvd channels): lvdl0 lvdl1 lvdl2 lvdh0 lvdh 1 lvdh2 - please use these lvd channels with your own risk - please monitor the external power supplies on the pcb if ne eded
document number: 002- 10635 rev.** page 163 of 247 s6j33 10/20/30/40 series preliminar * : for the connections of smoothing capacitor cs, see the following diagram. c pin connection diagram c s c v ss av ss d v ss ote ? the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the electrical characteristics of the device are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely af fect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact sales representatives beforehand. ? in the case of use in vcc5 = avcc5 = dvcc of conditions, please launch the power su pply in the following sequence. required power supply sequence is the following: vcc5 - > [dvcc or vcc53 or avcc5 or vcc3 or avcc3_dac] - > vcc12 note that power supplies inside "[ ]" can be turned on in arbitrary order. corresponding part number is s6j33xxxsb or s6j33xxxub or s6j33xxxtb or s6j33xxxvb or s6j33xxxb b or s6j33xxxd b or s6j33xxxf b or s6j33xxxh b. ? in the case of use in vcc5 = avcc5 < dvcc of conditions, please launch the power su pply in the following sequence. required power supply sequence is the following: vcc5 - > dvcc - > [vcc53 or avcc5 or vcc3 or avcc3_dac] - > vcc12. note that power supplies inside "[ ]" can be turned on in arbitrary order. corresponding part number is s6j33xxxab or s6j33xxxcb or s6j33xxxeb or s6j33xxxgb.
document number: 002- 10635 rev.** page 164 of 247 s6j33 10/20/30/40 series preliminar 9.1.3 dc characteristics (t a : recommended operating conditions, v cc 5,v cc 53=5.0v 10%, v cc 3=3.3v 0.3v, v ss =dv ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max "h" level input voltage v ih1 p0_00 to p0_20, p2_09 to p2_19, p3_00 to p3_07, p3_24 to p3_31, p4_00 to p4_07 cmos hysteresis input level is selected 0.7v cc 53 - v cc 53 +0.3 v v ih2 automotive input level is selected 0.8v cc 53 - v cc 53 +0.3 v v ih3 ttl input level is selected 2.0 - v cc 53 +0.3 v v ih4 p1_03 to p1_16, p3_08 to p3_23, p4_08 to p4_23 cmos hysteresis input level is selected 0.7v cc 5 - v cc 5 +0.3 v v ih5 automotive input level is selected 0.8v cc 5 - v cc 5 +0.3 v v ih6 p1_09, p1_10, p1_15, p1_16 input level is selected 2.0 - v cc 5 +0.3 v v ih7 p1_17 to p1_31, p2_00 to p2_08, p4_24 to p4_31 cmos hysteresis input level is selected 0.7dv cc - dv cc +0.3 v v ih8 automotive input level is selected 0.8dv cc - dv cc +0.3 v v ih9 rstx nmix 0.7v cc 5 - v cc 5 +0.3 v v ih10 0.7v cc 5 v cc 5 +0.3 v v ih11 jtag_n trs t jtag_ tck jtag_ tdi jtag_ tms 2. 7 - v cc 5 +0.3 v v ih12 p0_21 to p0_31, p1_00 to p1_02 cmos hysteresis input level is selected 0.7v cc 3 - v cc 3 +0.3 v v ih13 p0_21 to p0_31 ttl input level is selected 2.0 - v cc 3 +0.3 v v ih14 p1_00 to p1_02 1.7 v cc +0.3 v medialb
document number: 002- 10635 rev.** page 165 of 247 s6j33 10/20/30/40 series preliminar parameter symbol pin name conditions value unit remarks min typ max "l" level input voltage v il 1 p0_00 to p0_20, p2_09 to p2_19, p3_00 to p3_07, p3_24 to p3_31, p4_00 to p4_07 cmos hysteresis input level is selected vss - 0.3 - 0.3v cc 53 v v il 2 automotive input level is selected vss - 0.3 - 0.5v cc 53 v v il 3 ttl input level is selected vss - 0.3 - 0.8 v v il 4 p1_03 to p1_16, p3_08 to p3_23, p4_08 to p4_23 cmos hysteresis input level is selected vss - 0.3 - 0.3v cc 5 v v il 5 automotive input level is selected vss - 0.3 - 0.5v cc 5 v v il6 p1_09, p1_10, p1_15, p1_16 input level is selected vss - 0.3 - 0.8 v v il7 p1_17 to p1_31, p2_00 to p2_08, p4_24 to p4_31 cmos hysteresis input level is selected vss - 0.3 - 0.3dv cc v v il8 automotive input level is selected vss - 0.3 - 0.5dv cc v v il9 rstx nmix vss - 0.3 - 0.3v cc 5 v v il10 vss 0.3 0.3v cc 5 v v il11 jtag_n trs t jtag_ tck jtag_ tdi jtag_ tms vss - 0.3 - 0.8 v v il12 p0_21 to p0_31, p1_00 to p1_02 cmos hysteresis input level is selected vss - 0.3 - 0.3v cc 3 v v il13 p0_21 to p0_31 ttl input level is selected vss - 0.3 - 0.8 v v il14 p1_00 to p1_02 vss 0.3 0.7 v medialb
document number: 002- 10635 rev.** page 166 of 247 s6j33 10/20/30/40 series preliminar (t a : recommended operating conditions, v cc 5,v cc 53,dv cc =5.0v 10%, v cc 3=3.3v 0.3v, v ss =dv ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max "h" level output voltage v oh1 p0_00 to p0_19, p2_09 to p2_11, p2_13 to p2_19, p3_00 to p3_07, p3_24 to p3_31, p4_00 to p4_07 v cc 53=4.5 v , 2 - - 0.5 - v cc 53 v odr[1:0] =2b00 v cc 53=3.0 v , 2 - 2 v cc 53=4.5 v , 2 - - 0.5 - v cc 53 v odr[1:0] =2b01 v cc 53=3.0 v , 2 - 2 v cc 53=4.5 v , 2 - - 0.5 - v cc 53 v odr[1:0] =2b10 v cc 53=3.0 v , 2 - 2 p1_03 to p1_16, p3_08 to p3_23, p4_08 to p4_23 v cc 5=4.5 v , 2 - - 0.5 - v cc 5 v v oh5 v cc 5=4.5 v , 2 - - 0.5 - v cc 5 v v oh6 v cc 5=4.5 v , 2 - - 0.5 - v cc 5 v v oh7 psc_1 v cc 5=4.5 v , 2 - - 0.5 - v cc 5 v v oh8 jtag_ tdo v cc 5=4.5 v , 2 - - 0.5 - v cc 5 v v oh10 p1_17 to p1_31, p2_00 to p2_08, p4_24 to p4_31 dv cc =4.5 v , 2 - - 0.5 - dv cc v v oh11 dv cc =4.5 v , 2 - - 0.5 - dv cc v v oh12 dv cc =4.5 v , 2 - - 0.5 - dv cc v v oh13 dv cc =4.5 v , 2 - - 0.5 - dv cc v smc v oh14 dv cc =4.5 v , 2 - - 0.5 - dv cc v smc tj= 40 c v oh15 p0_21 to p0_31, p1_00 to p1_02 v cc 3=3.0 v , 2 - 3 - 0.5 - v cc 3 v v oh16 v cc 3=3.0 v , 2 - 3 - 0.5 - v cc 3 v v oh17 v cc 3=3.0 v , 2 - 3 - 0.5 - v cc 3 v v oh18 v cc 3=3.0 v , 2 - 3 - 0. 5 - v cc 3 v
document number: 002- 10635 rev.** page 167 of 247 s6j33 10/20/30/40 series preliminar parameter symbol pin name conditions value unit remarks min typ max "h" level output voltage v oh19 p2_12 v cc 53=4.5 v i oh = - 1.0 ma v cc 53 - 0.5 - v cc 53 v odr[1:0] =2b00 v oh20 v cc 53=3.0 v , 2 - 2 v cc 53=4.5 v , 2 - - 0.5 - v cc 53 v odr[1:0] =2b01 v oh22 v cc 53=3.0 v , 2 - 2 v cc 53=4.5 v , 2 - - 0.5 - v cc 53 v odr[1:0] =2b10 v oh24 v cc 53=3.0 v , 2 - 2 v cc 53=4.5 v , 2 - - 0.5 - vcc53 v odr[1:0] =2b11 v oh26 v cc 53=3.0 v , 2 -
document number: 002- 10635 rev.** page 168 of 247 s6j33 10/20/30/40 series preliminar (t a : recommended operating conditions, v cc 5,v cc 53,dv cc =5.0v 10%, v cc 3=3.3v 0.3v, v ss =dv ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max "l" level output voltage v ol1 p0_00 to p0_19, p2_09 to p2_11, p2_13 to p2_19, p3_00 to p3_07, p3_24 to p3_31, p4_00 to p4_07 v cc 53=4.5 v , 2/ - 0.4 v odr[1:0] =2b00 v cc 53=3.0 v , 2/ 2/ v cc 53=4.5 v , 2/ - 0.4 v odr[1:0] =2b01 v cc 53=3.0 v , 2/ 2/ v cc 53=4.5 v , 2/ - 0.4 v odr[1:0] =2b10 v cc 53=3.0 v , 2/ 2/ p1_03 to p1_16, p3_08 to p3_23, p4_08 to p4_23 v cc 5=4.5 v , 2/ - 0.4 v v ol5 v cc 5=4.5 v , 2/ - 0.4 v v ol6 v cc 5=4.5 v , 2/ - 0.4 v v ol7 psc_1 v cc 5=4.5 v , 2/ - 0.4 v v ol8 jtag_ tdo v cc 5=4.5 v , 2/ - 0.4 v v ol9 p1_09, p1_10, p1_15, p1_16 v cc 5=4.5 v , 2/ - 0.4 v i2c v ol10 p1_17 to p1_31, p2_00 to p2_08, p4_24 to p4_31 dv cc =4.5 v , 2/ - 0.4 v v ol11 dv cc =4.5 v , 2/ - 0.4 v v ol12 dv cc =4.5 v , 2/ - 0.4 v v ol13 dv cc =4.5 v , 2/ - 0.55 v smc v ol14 dv cc =4.5 v , 2/ - 0.55 v smc tj= 40 c v ol15 p0_21 to p0_31, p1_00 to p1_02 v cc 3=3.0 v , 2/ - 0.4 v v ol16 v cc 3=3.0 v , 2/ - 0.4 v v ol17 v cc 3=3.0 v , 2/ - 0.4 v v ol18 v cc 3=3.0 v , 2/ - 0.4 v
document number: 002- 10635 rev.** page 169 of 247 s6j33 10/20/30/40 series preliminar parameter symbol pin name conditions value unit remarks min typ max "l" level output voltage v ol19 p2_12 v cc 53=4.5 v i ol =1.0 ma 0 - 0.4 v odr[1:0] =2b00 v ol20 v cc 53=3.0 v , 2/ 2/ v cc 53=4.5 v , 2/ - 0.4 v odr[1:0] =2b01 v ol22 v cc 53=3.0 v , 2/ 2/ v cc 53=4.5 v , 2/ - 0.4 v odr[1:0] =2b10 v ol24 v cc 53=3.0 v , 2/ 2/ v cc 53=4.5 v , 2/ - 0.4 v odr[1:0] =2b11 v ol26 v cc 53=3.0 v , 2/
document number: 002- 10635 rev.** page 170 of 247 s6j33 10/20/30/40 series preliminar (t a : recommended operating conditions, v cc 5,v cc 53,dv cc =5.0v 10%, v cc 3=3.3v 0.3v, v ss =dv ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max input leakage current i il p0_00 to p0_20, p1_03 to p1_31, p2_00 to p2_19, p3_00 to p3_31, p4_00 to p4_31 av cc =5.5 v v ss < vi < v cc -5 - +5 a 5v pins 5v/3v pins p0_21 to p0_31, p1_00 to p1_02 v cc 3=3.6 v ss , 3 -10 - +10 a 3v pins pull -up resistor r up1 rstx, nmix 25 50 100 k r up2 p0_00 to p0_20, p1_03 to p1_31, p2_00 to p2_19, p3_00 to p3_31, p4_00 to p4_31 3 - up resistor selected 25 50 100 k 5v pins 5v/3v pins r up3 p0_21 to p0_31, p1_00 to p1_02 pull up resistor selected 17 50 66 k 3v pins r up4 jtag_tdi, jtag_tms, jtag_ tck - 25 50 100 k pull - down resistor r down1 p0_00 to p0_20, p1_03 to p1_31, p2_00 to p2_19, p3_00 to p3_31, p4_00 to p4_31 3 - down resistor selected 25 50 100 k 5v pins 5v/3v pins r down2 p0_21 to p0_31, p1_00 to p1_02 pull down resistor selected 17 50 66 k 3v pins r down3 jtag_n trs t 25 50 100 k input capacitance c in1 p0_00 to p0_31, p1_00 to p1_16, p2_09 to p2_19, p3_00 to p3_31, p4_00 to p4_23 - - 5 15 pf c in2 p1_17 to p1_31, p2_00 to p2_08, p4_24 to p4_31 - - 15 45 pf when using smc
document number: 002- 10635 rev.** page 171 of 247 s6j33 10/20/30/40 series preliminar (t a : recommended operating conditions, v cc 5,v cc 53,dv cc =5.0v 10%, v cc 3=3.3v 0.3v, v cc 12=1.1 5 v 0. 06v , v ss =dv ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max power supply current i cc12 vcc12 normal operation - 500 1000 ma t a = - a 33 (cpu:200mhz, hpm:200mhz) gdc : 200mhz flash write/erase - 550 1050 ma t a = - a 33 (cpu:200mhz, hpm:200mhz) gdc : 200mhz i cch12 timer/ stop mode 650 ma i cc5 vcc5 normal 45 85 ma flash write/erase 100 ma i cct5 timer mode - 370 810 a t a =25 system controllers. when using 4mhz crystal for main oscillator. - 360 780 a when shutting down 8kb backup ram i cch5 stop mode - 100 400 a t a =25
document number: 002- 10635 rev.** page 172 of 247 s6j33 10/20/30/40 series preliminar (t a : recommended operating conditions, v cc 5,v cc 53,dv cc =5.0v 10%, v cc 3=3.3v 0.3v, v cc 12=1. 15v 0. 06v , v ss =dv ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max high current output drive capacity phase - to - phase deviation1 delta -v oh13 pwm1pn, pwm1mn, pwm2pn, pwm2mn (n=0 to 5) dv cc =4.5v , 2 - 30.0ma maximum deviation of v oh13 - - 90 mv * high current output drive capacity phase - to - phase deviation2 delta -v ol13 dv cc =4.5v , 2/ maximum deviation of v ol13 - - 90 mv * lcd divider resistor r lcd v0 to v1, v1 to v2, v2 to v3 6.25 12.5 25 k com0 to com3 output impedance 2 comm (m=0 to 3) - - - 4.5 k seg00 to seg31 output impedance 6 segn (n=00 to 31) - - - 17 k lcdc leak current i lcdc v0 to v3, comm (m=0 to 3), segn (n=00 to 31) a =25 c - 0.5 - +0.5 a * : if pwm1p0/pwm1m0/pwm2p0/pwm2m0 of ch.0 is turned on simultaneously, the maximum deviation of v oh13 / v ol13 for each pin is defined. same for other channels.
document number: 002- 10635 rev.** page 173 of 247 s6j33 10/20/30/40 series preliminar 9.1.4 ac characteristics 9.1.4.1 source clock timing (t a : recommended operating conditions, vcc 5 =5.0 v 10%, v ss =dv ss =av ss =0.0 v) parameter symbo l pin name conditions value unit remarks min typ max source oscillation clock frequency fc x0, x1 - 3.6 - 4.0 mhz source oscillation clock cycle time tcyl x0, x1 - 250.0 - 277.8 ns can pll jitter (when locked) tpj - - -10 - 10 ns internal slow cr oscillation frequency fcrs - - 50 100 150 khz internal fast cr oscillation frequency fcrf - - 2.40 4.00 5.61 - mhz before 3.20 4.00 4.81 mhz after trim ? the maximum/minimum values have been standardized with the main clock and pll clock in use. ? jitter of source oscillator must be smaller than 300ppm. ? x0 and x1 clock timing x0 cyl can pll jitter a time difference from the ideal clock is guaranteed for each cycle period within 20,000 cycles. t1 t1 t2 t3 tn-1 tn tn-1 tn ideal clock slow pll output
document number: 002- 10635 rev.** page 174 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.2 sub clock timing (t a : recommended operating conditions, vcc 5 =5.0 v 10%, v ss =dv ss =av ss =0.0 v) parameter symbo l pin name conditions value unit remarks min typ max source oscillation clock frequency f cl x0a, x1a - - 32.768 - khz source oscillation clock cycle time lcyl x0a, x1a - - 30.52 - s ? x0a and x1a clock timing x0 a lc
document number: 002- 10635 rev.** page 175 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.3 internal clock timing ( S6J3310 ) ? this chapter shows the target characteristics for internal clock timing at the current stage. ? in the column symbol, same clock names as described in chapter 5: clock system of traveo tm platform hardware manual are used. ? corresponding functions for these cl ocks are described in chapter 5: clock configuration of s6j3300 series hardware manual. (t a : recommended operating conditions, v cc 5=5.0 v 10%, v cc 12=1. 15 v 0. 06v , v ss =0.0 v) parameter symbol value unit remarks max *1 max *2 max *3 internal clock frequency f sscg0 480 400 360 mhz sscg0 output clock sscg1 400 400 400 mhz sscg 1 output clock sscg2 320 320 320 mhz sscg output clock sscg3 400 400 400 mhz sscg output clock pll0 480 400 360 mhz pll 0 output clock pll1 400 400 400 mhz pll1 output clock pll2 400 400 400 mhz pll2 output clock pll3 4 8 0 4 8 0 4 8 0 mhz pll3 output clock clk_cpu0 240 200 180 mhz clk_she 240 200 180 mhz clk_fclk 80 66.7 90 mhz clk_atb 120 100 90 mhz clk_dbg 120 100 90 mhz clk_hpm 120 200 180 mhz clk_hpm2 60 100 90 mhz clk_dma 120 200 180 mhz clk_memc 120 200 180 mhz clk_extbus 40 40 30 mhz clk_sysc1 40 40 60 mhz clk_happ0a0 40 40 30 mhz unused clk_happ0a1 40 40 30 mhz unused clk_happ1b0 60 50 60 mhz clk_happ1b1 40 50 30 mhz unused clk_llpbm 240 200 180 mhz clk_llpbm2 120 100 90 mhz clk_lcp 80 50 60 mhz clk_lcp0 40 40 30 mhz clk_lcp0a 80 66.7 60 mhz clk_lcp1 40 40 30 mhz unused clk_lcp1a 80 66.7 60 mhz clk_lapp0 40 40 30 mhz unused clk_lapp0a 40 40 30 mhz unused clk_lapp1 40 40 30 mhz unused clk_lapp1a 40 40 30 mhz unused clk_trc 1 00 1 00 100 mhz clk_cd1 200 200 200 mhz clk_cd1a0 100 100 100 mhz unused clk_cd1a1 100 100 100 mhz unused clk_cd1b0 100 100 100 mhz unused clk_cd1b1 100 100 100 mhz unused clk_cd2 200 200 200 mhz unused clk_cd2a0 200 200 200 mhz clk_cd2a1 200 200 200 mhz unused clk_cd2b0 200 200 200 mhz unused clk_cd2b1 200 200 200 mhz unused clk_cd3 80 80 8 0 mhz unused clk_cd3a0 80 80 8 0 mhz clk_cd3a1 80 80 8 0 mhz unused
document number: 002- 10635 rev.** page 176 of 247 s6j33 10/20/30/40 series preliminar parameter symbol value unit remarks max *1 max *2 max *3 internal clock frequency f clk_cd3b0 80 80 8 0 mhz unused clk_cd3b1 80 80 8 0 mhz unused clk_cd4 200 200 200 mhz clk_cd4a0 200 200 200 mhz unused clk_cd4a1 200 200 200 mhz unused clk_cd4b0 200 200 200 mhz unused clk_cd4b1 200 200 200 mhz unused clk_cd5 240 240 240 mhz clk_cd5a0 120 120 120 mhz clk_cd5a1 120 120 120 mhz unused clk_cd5b0 60 60 0 mhz clk_cd5b1 60 60 60 mhz unused clk_hsspi 200 200 200 mhz clk_sysc0h 80 66.7 60 mhz clk_comh 80 66.7 60 mhz clk_ram0h 80 66.7 60 mhz clk_ram1h 80 66.7 60 mhz clk_sysc0p 80 66.7 60 mhz clk_comp 80 66.7 60 mhz *1: target maximum clock frequencies when cpu clock = 240mhz * 2 : target maximum clock frequencies when cpu clock = 2 0 0mhz *3: target maximum clock frequencies when cpu clock = 18 0mhz - note that ta=125 condition is not supported in this product type. when using ss cg_pll output for these internal clock, the max value of frequency has the following restrictions. \ on the presumption that the modulation mode of sscg_pll is used with down spread, the max value of the frequency is standardized. \ this means that max value of frequency is the maximum value when sscg_pll was modulated.
document number: 002- 10635 rev.** page 177 of 247 s6j33 10/20/30/40 series preliminar ? operation assurance range relationship between the internal clock frequency and supply voltage note: cpu will be reset, when the power supply voltage is equal to or less than lvd setting voltage. 5.5 4.5 3.5 4 maximum frequency of each clock frequency [mhz] power supply v cc 5 [v] 2 dltqf dfff frequency [mhz] power supply v cc 12 > fqggddqg sdlqdq guaranteed operation range pll guaranteed operation range
document number: 002- 10635 rev.** page 178 of 247 s6j33 10/20/30/40 series preliminar ? relationship between the oscillation clock frequency and internal clock frequency internal operation clock frequency main clock pll clock multiplied by 1 multiplied by 2 multiplied by 3 multiplied by 4 multiplied by 40 multiplied by 60 oscillation clock frequency [mhz] 4 2 4 8 12 16 160 240 ? oscillation circuit example note: for the configuration of an oscillation circuit, request the oscillator manufacturer to perform a circuit matching evaluation before starting design. ac characteristics are specified by the following measurement reference voltage values. ? input signal waveform ? output signal wavefor m hysteresis input pin (automotive) 0.5v cc 5 0.8v cc 5 output pin 0.8v 2.4v hysteresis input pin (cmos schmitt) 0.3v cc 5 0.7v cc 5 0.3v cc 0.7v cc hysteresis input pin (ttl) 0. 8 v 2.0 v x1 x0 r c 2 c 1
document number: 002- 10635 rev.** page 179 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.4 reset input (t a : recommended operating conditions, vcc5=5.0 v 10%, v ss =0.0 v) parameter symbol pin name conditions value unit remarks min max reset input time t rstl rstx - 10 - s width for reset input removal 1 - s rstx 0. vcc 0. vcc rstl
document number: 002- 10635 rev.** page 180 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.5 power - on conditions (t a : recommended operating conditions, v ss =0.0 v) parameter symbol pin name condition s value unit remarks min typ max level detection voltage - vcc5 - 2.2 2.4 2.6 v level detection hysteresis width vcc5 - - 100 - mv level detection 40 s *1 power off time - vcc5 - 50 - - ms * 2 power ramp rate dv/dt vcc5 vcc 5 : 0.2v to 2.6v - - 1 v/s * 3 maximum ramp rate guaranteed to not generate power - on reset gg vcc5 vcc 5 : between 2.4v and 4 .5v 50 mv/s * 4 *1: this specification is at 1v/s of power ramp rate. *2: vcc5 must be held below 0.2v for a minimum period of t off . *3: power ramp rate must be 1v/us or less from 0.2v to 2.6v. power - on can detect by satisfying power ramp rate wh en power off time is satisfied. * 4 : this specification is specified the power supply fluctuation after power on detection. when vcc 5 voltage is between 2.4v and 4 .5v, the power supply fluctuation is below 50mv/us, the detection of power - on is suppressed. the power - on d oes not detect in any power fluctuation between 4.5v and 5.5v. otes when using S6J3310/20/30/40, *2 and *3 must be satisfied. when neither *2 nor *3 can be s atisfied, assert external reset (rstx) at power up and any brownout event. ? power off time, power ramp rate v cc off 0.2 v 0.2 v dv/dt 2.6 v ? undetected p ower ramp rate v cc .4 v dv/dt 5.5v dv/dt 4 . 5 v
document number: 002- 10635 rev.** page 181 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.6 multi - function serial uart (asynchronous serial interface) timing (smr:md2 - 0=0b000, 0b001) (1) external clock selected (bgr:ext=1) (t a : recommended operating conditions, vcc3=3.3 v 0.3v, vcc5=dvcc=5.0 v 10% /3.3 v 0.3v , vcc53=5.0 v 10% / 3.3 v 0.3v, v ss =dv ss =0.0 v, v cc 12=1. 15v 0. 06v ) parameter symbol pin name condition s value unit remarks min max serial clock "l" pulse width t slsh sck0 to sck4, sck8 to sck12 - t clk_lcpna *1 +10 - ns sck16 to sck17 t clk_comp +10 - ns serial clock "h" pulse width t shsl sck0 to sck4, sck8 to sck12 t clk_lcpna *1 +10 - ns sck16 to sck17 t clk_comp +10 - ns sck falling time t f sck0 to sck4, sck8 to sck12, sck16 to sck17 - 5 ns sck rising time t r - 5 ns *1: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12 external clock selected sck t shsl v il
document number: 002- 10635 rev.** page 182 of 247 s6j33 10/20/30/40 series preliminar csio timing (smr:md2 - 0=0b010) (1) normal synchronous transfer (scr:spi=0) and mark level "h" of serial clock output (smr:scinv=0) (t a : recommended operating conditions, vcc3=3.3 v 0.3v, vcc5=dvcc=5.0 v 10% /3.3 v 0.3v, vcc53=5.0 v 10% / 3.3 v 0.3v, v ss =dv ss =0.0 v, v cc 12=1. 15v 0. 06v ) parameter symbol pin name condition s value unit remarks min max serial clock cycle time t scyc sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12 master mode (cl = 2 0 pf, i ol = -5 ma, i oh = 5 ma) 8 t clk_lcpna *1 - ns - sck16 to sck17 8 t clk_comp - ns sck sot delay time t slovi sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12, sck16 to sck17 sot0, sot1, sot2_1, sot3_1, sot4, sot8 to sot12, sot16 to sot17 -30 + 30 ns valid sin sck setup time t ivshi sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12, sck16 to sck17 sin0, sin1, sin2_1, sin3_1, sin4, sin8 to sin12, sin16 to sin17 40 - ns sck valid sin hold time t shixi 0 - ns serial clock cycle time t scyc sck2_0, sck3_0 master mode (cl = 20pf, i ol = - 10ma, i oh =10ma) 2t clk_lcpna *1 - ns - sck sot delay time t slovi sck2_0, sck3_0, sot2_0, sot3_0 - 7.5 + 7.5 ns valid sin sck setup time ivshi sck2_0, sck3_0, sin2_0, sin3_0 10 - ns sck valid sin hold time t shixi 0 - ns
document number: 002- 10635 rev.** page 183 of 247 s6j33 10/20/30/40 series preliminar parameter symbol pin name condition s value unit remarks min max serial clock "h" pulse width t shsl sck0 to sck4, sck8 to sck12 slave mode (cl= 2 0 pf, i ol = -5 ma, i oh = 5 ma) 4 t clk_lcpna *1 - ns - sck16 to sck17 4 t clk_comp - ns serial clock "l" pulse width t slsh sck0 to sck4, sck8 to sck12 4 t clk_lcpna *1 - ns sck16 to sck17 4 t clk_comp - ns sck sot delay time t slove sck0 to sck4, sck8 to sck12, sck16 to sck17 sot0 to sot4, sot8 to sot12, sot16 to sot17 - 40 ns valid sin sck setup time ivshe sck0 to sck4, sck8 to sck12, sck16 to sck17 sin0 to sin4, sin8 to sin12, sin16 to sin17 10 - ns sck valid sin hold time shixe 10 - ns sck falling time t f sck0 to sck4, sck8 to sck12, sck16 to sck17 5 ns sck rising time t r sck0 to sck4, sck8 to sck12, sck16 to sck17 5 ns *1: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12 otes ? this table provides the alternate current standard for clk synchronous mode. ? cl is the load capability value connected to the pin at the test time. ? the maximum baud rate is limited by the internal operating clock used and other parameters. for details, see the hardware manual.
document number: 002- 10635 rev.** page 184 of 247 s6j33 10/20/30/40 series preliminar master mode t scyc v ol t slovi t s t s l l s st s l slave mode t slsh v i l t slove t ivshe t shixe v ih v il v oh v ol sck sot sin v ih v il t f v ih v i l v ih t shsl t r v ih
document number: 002- 10635 rev.** page 185 of 247 s6j33 10/20/30/40 series preliminar (2) normal synchronous transfer (scr:spi=0) and mark level "l" of serial clock output (smr:scinv=1) (t a : recommended operating conditions, vcc3=3.3 v 0.3v, vcc5=dvcc=5.0 v 10% /3.3v 0.3v, vcc53=5.0 v 10% / 3.3 v 0.3v, v ss =dv ss =0.0 v, v cc 12=1. 15v 0. 06v ) parameter symbol pin name condition s value unit remarks min max serial clock cycle time t scyc sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12 mode (cl = 2 0 pf, i ol = -5 ma, i oh = 5 ma) 8 t clk_lcpna *1 - ns master mode (cl = 2 0 pf, i ol = -5 ma, i oh = 5 ma) sck16 to sck17 8 clk_comp sck sot delay time t shovi sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12, sck16 to sck17 sot0, sot1, sot2_1, sot3_1, sot4, sot8 to sot12, sot16 to sot17 30 + 30 ns @20mhz @16mhz @12.5mhz valid sin sck setup time t ivsli sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12, sck16 to sck17 sin0, sin1, sin2_1, sin3_1, sin4, sin8 to sin12, sin16 to sin17 4 0 - ns @20mhz @16mhz @12.5mhz sck valid sin hold time t slixi 0 - ns
document number: 002- 10635 rev.** page 186 of 247 s6j33 10/20/30/40 series preliminar parameter symbol pin name condition s value unit remarks min max serial clock cycle time t scyc sck2_0, sck3_0 master mode (cl = 20pf, i ol = - 10ma, i oh =10ma) 2t clk_lcpna *1 - ns master mode (cl = 20pf, i ol = - 10ma, i oh =10ma) sck sot delay time shovi sck2_0, sck3_0, sot2_0, sot3_0 7.5 + 7.5 ns valid sin sck setup time ivsli sck2_0, sck3_0, sin2_0, sin3_0 10 - ns sck valid sin hold time slixi 0 - ns serial clock "h" pulse width t shsl sck0 to sck4, sck8 to sck12 mode (cl= 2 0 pf, i ol = -5 ma, i oh = 5 ma) 4 t clk_lcpna *1 - ns slave mode (cl= 2 0 pf, i ol = -5 ma, i oh = 5 ma) sck16 to sck17 4 clk_comp serial clock "l" pulse width t slsh sck0 to sck4, sck8 to sck12 4 t clk_lcpna *1 - ns sck16 to sck17 4 clk_comp sck sot delay time t shove sck0 to sck4, sck8 to sck12, sck16 to sck17 sot0 to sot4, sot8 to sot12, sot16 to sot17 40 ns @20mhz @16mhz @12.5mhz valid sin sck setup time ivsle sck0 to sck4, sck8 to sck12, sck16 to sck17 sin0 to sin4, sin8 to sin12, sin16 to sin17 10 - ns sck valid sin hold time slixe 10 - ns sck falling time t f sck0 to sck4, sck8 to sck12, sck16 to sck17 5 ns sck rising time t r sck0 to sck4, sck8 to sck12, sck16 to sck17 5 ns *1: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12 otes ? this table provides the alternate current standard for clk synchronous mode. ? cl is the load capability value connected to the pin at the test time. ? the maximum baud rate is limited by the internal operating clock used and other parameters. for details, see the hardware manual.
document number: 002- 10635 rev.** page 187 of 247 s6j33 10/20/30/40 series preliminar master mode t scyc v oh t shovi t ivsli t slixi v ih v il v oh v ol sck sot sin v ih v il v ol slave mode t shsl v i l t shove t ivsle t slixe v ih v il v oh v ol sck sot sin v ih v il t r v ih v i l v ih t slsh t f v i l
document number: 002- 10635 rev.** page 188 of 247 s6j33 10/20/30/40 series preliminar (3) spi supported (scr:spi=1), and mark level "h" of serial clock output (smr:scinv=0) (t a : recommended operating conditions, vcc3=3.3 v 0.3v%, vcc5=dvcc=5.0v 10% /3.3 v 0.3v, vcc53=5.0 v 10% / 3.3 v 0.3v, v ss =dv ss =0.0 v, v cc 12=1. 15v 0. 06v ) parameter symbol pin name condition s value unit remarks min max serial clock cycle time t scyc sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12 mode (cl = 2 0 pf, i ol = -5 ma, i oh = 5 ma) 8 t clk_lcpna *1 - ns - sck16 to sck17 8 clk_comp sck sot delay time t shovi sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12, sck16 to sck17 sot0, sot1, sot2_1, sot3_1, sot4, sot8 to sot12, sot16 to sot17 30 + 30 ns valid sin sck setup time ivsli sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12, sck16 to sck17 sin0, sin1, sin2_1, sin3_1, sin4, sin8 to sin12, sin16 to sin17 4 0 - ns sck valid sin hold time t slixi 0 - ns sot sck delay time t sovli sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12, sck16 to sck17 sot0, sot1, sot2_1, sot3_1, sot4, sot8 to sot12, sot16 to sot17 4 t clk_lcpna *1 -30 - ns sck16 to sck17 sot16 to sot17 4 t clk_comp *1 -30 - ns - serial clock scyc sck2_0, sck3_0 master mode (cl = 20pf, i ol = - 10ma, i oh =10ma) 2t clk_lcpna *1 - ns - sck sot delay time shovi sck2_0, sck3_0, sot2_0, sot3_0 7.5 + 7.5 ns valid sin sck setup time ivshi sck2_0, sck3_0, sin2_0, sin3_0 10 - ns sck valid sin hold time shixi 0 - ns sot sck delay time sovli sck2_0, sck3_0, sot2_0, sot3_0 clk_lcp n a *1 - - ns
document number: 002- 10635 rev.** page 189 of 247 s6j33 10/20/30/40 series preliminar parameter symbol pin name condition s value unit remarks min max serial clock "h" pulse width t shsl sck0 to sck4, sck8 to sck12 mode (cl= 2 0 pf, i ol = -5 ma, i oh = 5 ma) 4 t clk_lcpna *1 - ns sck16 to sck17 4 clk_comp serial clock "l" pulse width t slsh sck0 to sck4, sck8 to sck12 4 t clk_lcpna *1 - ns sck16 to sck17 4 clk_comp sck sot delay time t shove sck0 to sck4, sck8 to sck12, sck16 to sck17 sot0 to sot4, sot8 to sot12, sot16 to sot17 40 ns valid sin sck setup time ivsle sck0 to sck4, sck8 to sck12, sck16 to sck17 sin0 to sin4, sin8 to sin12, sin16 to sin17 10 - ns sck valid sin hold time slixe 10 - ns sck falling time t f sck0 to sck4, sck8 to sck12 sck16 to sck17 5 ns sck rising time t r sck0 to sck4, sck8 to sck12 sck16 to sck17 5 ns *1: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12 otes ? this table provides the alternate current standard for clk synchronous mode. ? cl is the load capability value connected to the pin at the test time. ? the maximum baud rate is limited by the internal operating clock used and other parameters. for details, see the hardware manual. master mode t scyc v ol t sovli t slixi v ih v il v oh v ol sck sot sin v ih v il v oh v oh v ol t ivsli t shovi v ol
document number: 002- 10635 rev.** page 190 of 247 s6j33 10/20/30/40 series preliminar slave mode t slsh v i l t f t slixe v ih v il v oh v ol sck sot sin v ih v il v ih v oh v ol t ivsle t shove v i l v ih v ih v i l t shsl t r * * changes when writing to the tdr register
document number: 002- 10635 rev.** page 191 of 247 s6j33 10/20/30/40 series preliminar (4) spi supported (scr:spi=1), and mark level "l" of serial clock output (smr:scinv=1) (t a : recommended operating conditions, vcc3=3.3 v 0.3v, vcc5=dvcc=5.0 v 10% /3.3v 0.3v, vcc53=5.0 v 10% / 3.3 v 0.3v, v ss =dv ss =0.0 v, v cc 12=1. 15v 0. 06v ) parameter symbol pin name condition s value unit remarks min max serial clock cycle time t scyc sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12 mode (cl = 2 0 pf, i ol = -5 ma, i oh = 5 ma) 8 t clk_lcpna *1 - ns - sck16 to sck17 8 clk_comp sck - > sot delay time t slovi sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12, sck16 to sck17 sot0, sot1, sot2_1, sot3_1, sot4, sot8 to sot12, sot16 to sot17 30 + 30 ns valid sin - > sck setup time t ivshi sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12, sck16 to sck17 sin0, sin1, sin2_1, sin3_1, sin4, sin8 to sin12, sin16 to sin17 4 0 - ns sck - > valid sin hold time t shixi 0 - ns sot - > sck delay time t sovhi sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12, sck16 to sck17 sot0, sot1, sot2_1, sot3_1, sot4, sot8 to sot12, sot16 to sot17 4 t clk_lcpna *1 -30 - ns sck16 to sck17 sot16 to sot17 4 clk_comp - - ns serial clock scyc sck2_0, sck3_0 master mode (cl = 20pf, i ol = - 10ma, i oh =10ma) 2t clk_lcpna *1 - ns - sck > sot delay time slovi sck2_0, sck3_0, sot2_0, sot3_0 7.5 + 7.5 ns valid sin sck setup time ivshi sck2_0, sck3_0, sin2_0, sin3_0 10 - ns sck > valid sin hold time shixi 0 - ns sot - > sck delay time t sovhi sck2_0, sck3_0, sot2_0, sot3_0 t clk_lcp n a *1 - 7.5 - ns
document number: 002- 10635 rev.** page 192 of 247 s6j33 10/20/30/40 series preliminar parameter symbol pin name condition s value unit remarks min max serial clock "h" pulse width t shsl sck0 to sck4, sck8 to sck12 mode (cl= 2 0 pf, i ol = -5 ma, i oh = 5 ma) 4 t clk_lcpna *1 - ns - sck16 to sck17 4 clk_comp serial clock "l" pulse width t slsh sck0 to sck4, sck8 to sck12 4 t clk_lcpna *1 - ns sck16 to sck17 4 clk_comp sck - > sot delay time t slove sck0 to sck4, sck8 to sck12, sck16 to sck17 sot0 to sot4, sot8 to sot12, sot16 to sot17 40 ns valid sin > sck setup time ivshe sck0 to sck4, sck8 to sck12, sck16 to sck17 sin0 to sin4, sin8 to sin12, sin16 to sin17 10 - ns sck - > valid sin hold time t shixe 10 - ns sck falling time t f sck0 to sck4, sck8 to sck12 sck16 to sck17 5 ns sck rising time t r sck0 to sck4, sck8 to sck12 sck16 to sck17 5 ns *1: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12 otes ? this table provides the alternate current standard for clk synchronous mode. ? cl is the load capability value connected to the pin at the test time. ? the maximum baud rate is limited by the internal operating clock used and other parameters. for details, see the hardware manual. master mode t scyc v oh t sovhi t shixi v ih v il v oh v ol sck sot sin v ih v il v ol v oh v ol t ivshi t slovi v oh
document number: 002- 10635 rev.** page 193 of 247 s6j33 10/20/30/40 series preliminar slave mode t shsl v i l t r t shixe v ih v il v oh v ol sck sot sin v ih v il v ih v oh v ol t ivshe t slov v i l v ih v ih v i l t slsh t f * * changes when writing to the tdr register
document number: 002- 10635 rev.** page 194 of 247 s6j33 10/20/30/40 series preliminar (5) serial chip select used (scscr:csen=1) ? mark level "h" of serial clock output (smr, scsfr:scinv=0) ? inactive level "h" of serial chip select (scscr, scsfr:cslvl=1) (ta: recommended operating conditions, vcc3=3.3 v 0.3v%, vcc5=dvcc=5.0 v 10% /3.3v 0.3v, vcc53=5.0 v 10% / 3.3 v 0.3v, v ss =dv ss =0.0 v, v cc 12=1. 15v 0. 06v ) parameter symbol pin name condition s value unit remarks min max scs sck setup time t cssi sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12, sck16 to sck17 scs0x, scs1x, scs2x_1, scs3x_1, scs4, scs8x to scs12x, scs16x to scs17x mode (cl = 2 0 pf, i ol = -5 ma, i oh = 5 ma) t cssu *1 -15 - ns sck scs hold time t cshi t cshd *2 +0 - ns scs deselect time t csdi scs0x, scs1x, scs2x_1, scs3x_1, scs4, scs8x to scs12x csds *3 -15 +5t clk_lcpna *4 - ns scs16x to scs17x t csds *3 - /23 - ns scs sck setup time cssi sck2_0, sck3_0, scs2x_0, scs3x_0 master mode (cl = 20pf, i ol = - 10ma, i oh =10ma) t cssu *1 -10 - ns sck scs hold time cshi t cshd *2 +0 - ns scs deselect time csdi scs2x_0, scs3x_0 t csds *3 - //3q - ns scs sck setup time t csse sck0 to sck4, sck8 to sck12 scs0x to scs4x, scs8x to scs12x mode (cl= 2 0 pf, i ol = -5 ma, i oh = 5 ma) 4 t clk_lcpna *4 +15 - ns sck16 to sck17, scs16x to scs17x 4 clk_comp - ns sck scs hold time t cshe sck0 to sck4, sck8 to sck12, sck16 to sck17, scs0x to scs4x, scs8x to scs12x, scs16x to scs17x 0 - ns scs deselect time t csde scs0x to scs4x, scs8x to scs12x 4 clk_lcpna *4 - ns scs16x to scs17x 4 clk_comp - ns scs sot delay time scs0x to scs4x, scs8x to scs12x, scs16x to scs17x, sot0 to sot4, sot8 to sot12, sot16 to sot17 40 ns scs sot delay time t dee 0 - ns
document number: 002- 10635 rev.** page 195 of 247 s6j33 10/20/30/40 series preliminar parameter symbol pin name condition s value unit remarks min max sck scs clock switching time t scc sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12, scs0x, scs1x, scs2x_1, scs3x_1, scs4, scs8x to scs12x mode round operation (cl=20pf, i ol = -5 ma, i oh = 5 ma) 4 t clk_lcpna *4 +0 4 t clk_lcpna * 4 +15 ns sck16 to sck17 scs16x to scs17x 4 t clk_comp +0 4 clk_comp +15 sck2_0, sck3_0, scs2x_0, scs3x_0 master mode round operation (cl = 20pf, i ol = - 10ma, i oh =10ma) 4 t clk_lcpna *4 +0 4 t clk_lcpna * 4 +10 ns *1: t cssu =scstr:cssu[7:0] x serial chip select timing operating clock *2: t cshd =scstr:cshd[7:0] x serial chip select timing operating clock *3: t csds =scstr:csds[15:0] x serial chip select timing operating clock for details on *1 , *2 , and *3 above, see the hardware manual. *4 t clk_lcpna n=0:ch.0 to ch.4, n=1:ch.8 to ch.12 otes ? this is the ac characteristic in clk synchronized mode. ? cl is the load capacitance applied to pins during testing. ? the maximum baud r ate is limited by the internal operating clock used and other parameters. for details, see the hardware manual. master mode sck output sot (normal synchronous transfer) sot (spi compatible ) t cssi scs output t cshi t csdi v ol v ol v ol v oh v oh v oh
document number: 002- 10635 rev.** page 196 of 247 s6j33 10/20/30/40 series preliminar slave mode sck input sot (normal synchronous transfer) sot (spi compatible ) t csse scs input t cshe t csde t dse t dee v il v il v ih v ih v il v ih v ol v ol v oh clock switching example by master mode round operation (x,y = 0, 1, 2, 3 : x and y are different value) scsy output sck output scsx output t scc v ol v ol
document number: 002- 10635 rev.** page 197 of 247 s6j33 10/20/30/40 series preliminar (6) serial chip select used (scscr:csen=1) ? serial clock output signal detect level "l" (smr, scsfr:scinv=1) ? serial chip select inactive level "h" (scscr, scsfr:cslvl=1) (ta: recommended operating conditions, vcc3=3.3 v 0.3v%, vcc5=dvcc=5.0 v 10% /3.3v 0.3v, vcc53=5.0 v 10% / 3.3 v 0.3v, v ss =dv ss =0.0 v, v cc 12=1. 15v 0. 06v ) parameter symbol pin name condition s value unit remarks min max scs sck setup time t cssi sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12, sck16 to sck17 scs0x, scs1x, scs2x_1, scs3x_1, scs4, scs8x to scs12x, scs16x to scs17x mode (cl= 2 0 pf, i ol = -5 ma, i oh = 5 ma) t cssu *1 -15 - ns sck scs hold time t cshi t cshd *2 +0 - ns scs deselect time t csdi scs0x, scs1x, scs2x_1, scs3x_1, scs4, scs8x to scs12x csds *3 -15 +5 t clk_lcpna *4 - ns scs16x to scs17x t csds *3 - /23 - ns scs sck setup cssi sck2_0, sck3_0, scs2x_0, scs3x_0 master mode (cl = 20pf, i ol = - 10ma, i oh =10ma) t cssu *1 -10 - ns sck scs hold time cshi t cshd *2 +0 - ns scs deselect time csdi scs2x_0, scs3x_0 t csds *3 - //3q - ns scs sck setup time t csse sck0 to sck4, sck8 to sck12, scs0x to scs4x, scs8x to scs12x mode (cl= 2 0 pf, i ol = -5 ma, i oh = 5 ma) 4 t clk_lcpna *4 +15 - ns sck16 to sck17, scs16x to scs17x 4 clk_comp - ns sck scs hold time t cshe sck0 to sck4, sck8 to sck12, sck16 to sck17, scs0x to scs4x, scs8x to scs12x, scs16x to scs17x 0 - ns scs deselect time t csde scs0x to scs4x, scs8x to scs12x 4 clk_lcpna *4 - ns scs16x to scs17x 4 clk_comp - ns scs sot delay time scs0x to scs4x, scs8x to scs12x, scs16x to scs17x, sot0 to sot4, sot8 to sot12, sot16 to sot17 40 ns scs sot delay time t dee 0 - ns
document number: 002- 10635 rev.** page 198 of 247 s6j33 10/20/30/40 series preliminar parameter symbol pin name condition s value unit remarks min max sck scs clock switching time t scc sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12, scs0x, scs1x, scs2x_1, scs3x_1, scs4, scs8x to scs12x mode round operation (cl= 2 0 pf, i ol = -5 ma, i oh = 5 ma) 4 t clk_lcpna *4 +0 4 t clk_lcpna * 4 +15 ns sck16 to sck17 scs16x to scs17x 4 t clk_comp +0 4 clk_comp ns sck2_0, sck3_0, scs2x_0, scs3x_0 master mode round operation (cl = 20pf, i ol = - 10ma, i oh =10ma) 4 t clk_lcpna *4 +0 4 t clk_lcpna * 4 +10 ns *1: t cssu =scstr:cssu[7:0] x serial chip select timing operating clock *2: t cshd =scstr:cshd[7:0] x serial chip select timing operating clock *3: t csds =scstr:csds[15:0] x serial chip select timing operating clock for details on *1 , *2 , and *3 above, see the hardware manual. *4 t clk_lcpna n=0:ch.0 to ch.4, n=1:ch.8 to ch.12 otes ? this is the ac characteristic in clk synchronized mode. ? cl is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by the internal operating clock used and other parameters. for details, see the hardware manual. master mode sck output sot (normal synchronous transfer) sot (spi compatible ) t cssi scs output t cshi t csdi v ol v ol v oh v oh v oh v ol
document number: 002- 10635 rev.** page 199 of 247 s6j33 10/20/30/40 series preliminar slave mode sck input sot (normal synchronous transfer) sot (spi compatible ) t csse scs input t cshe t csde t dse t dee v il v il v ih v ih v ih v il v o l v o l v oh clock switching example by master mode round operation (x,y= 0, 1, 2, 3 : x and y are different value) scsy output sck output scsx output t scc v ol v oh
document number: 002- 10635 rev.** page 200 of 247 s6j33 10/20/30/40 series preliminar (7) serial chip select used (scscr:csen=1) ? serial clock output signal detect level "h" (smr, scsfr:scinv=0) ? serial chip select inactive level "l" (scscr, scsfr:cslvl=0 (ta: recommended operating conditions, vcc3=3.3 v 0.3v%, vcc5=dvcc=5.0 v 10% /3.3v 0.3v, vcc53=5.0 v 10% / 3.3 v 0.3v, v ss =dv ss =0.0 v , v cc 12=1. 15v 0. 06v ) parameter symbol pin name conditions value unit remarks min max scs sck setup time t cssi sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12, sck16 to sck17 scs0x, scs1x, scs2x_1, scs3x_1, scs4, scs8x to scs12x, scs16x to scs17x mode (cl= 2 0 pf, i ol = -5 ma, i oh = 5 ma) t cssu *1 -15 - ns sck scs hold time t cshi t cshd *2 +0 - ns scs deselect time t csdi scs0x, scs1x, scs2x_1, scs3x_1, scs4, scs8x to scs12x csds *3 -15 +5 t clk_lcpna *4 - ns scs16x to scs17x t csds *3 - /23 - ns scs sck setup cssi sck2_0, sck3_0, scs2x_0, scs3x_0 master mode (cl = 20pf, i ol = - 10ma, i oh =10ma) t cssu *1 -10 - ns sck scs hold time cshi t cshd *2 +0 - ns scs deselect time csdi scs2x_0, scs3x_0 t csds *3 - //3q - ns scs sck setup time t csse sck0 to sck4, sck8 to sck12 scs0x to scs4x, scs8x to scs12x mode (cl= 2 0 pf, i ol = -5 ma, i oh = 5 ma) 4 t clk_lcpna *4 +15 - ns sck16 to sck17, scs16x to scs17x 4 clk_comp - ns sck scs hold time t cshe sck0 to sck4, sck8 to sck12, sck16 to sck17, scs0x to scs4x, scs8x to scs12x, scs16x to scs17x 0 - ns scs deselect time t csde scs0x to scs4x, scs8x to scs12x 4 clk_lcpna *4 - ns scs16x to scs17x 4 clk_comp - ns scs sot delay time scs0x to scs4x, scs8x to scs12x, scs16x to scs17x, sot0 to sot4, sot8 to sot12, sot16 to sot17 40 ns scs sot delay time t dee 0 - ns
document number: 002- 10635 rev.** page 201 of 247 s6j33 10/20/30/40 series preliminar parameter symbol pin name conditions value unit remarks min max sck scs clock switching time t scc sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12 scs0x, scs1x, scs2x_1, scs3x_1, scs4, scs8x to scs12x mode round operation (cl= 2 0 pf, i ol = -5 ma, i oh = 5 ma) 4 t clk_lcpna *4 +0 4 t clk_lcpna * 4 +15 ns sck16 to sck17 scs16x to scs17x 4 t clk_comp +0 4 clk_comp ns sck2_0, sck3_0, scs2x_0, scs3x_0 master mode round operation (cl = 20pf, i ol = - 10ma, i oh =10ma) 4 t clk_lcpna *4 +0 4 t clk_lcpna * 4 +10 ns *1: t cssu =scstr:cssu[7:0] x serial chip select timing operating clock *2: t cshd =scstr:cshd[7:0] x serial chip select timing operating clock *3: t csds =scstr:csds[15:0] x serial chip select timing operating clock for details on *1 , *2 , and *3 above, see the hardware manual. *4 t clk_lcpna n=0:ch.0 to ch.4, n=1:ch.8 to ch.12 otes ? this is the ac characteristic in clk synchronized mode. ? cl is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by the internal operating clock used and other parameters. for details, see the hardware manual master mode sck output sot (normal synchronous transfer) sot (spi compatible ) t cssi scs output t cshi t csdi v oh v ol v oh v oh v ol
document number: 002- 10635 rev.** page 202 of 247 s6j33 10/20/30/40 series preliminar slave mode sck input sot (normal synchronous transfer) sot (spi compatible ) t csse scs input t cshe t csde t dse t dee v ih v ih v il v ih v il c lock switching example by master mode round operation (x,y=0, 1, 2, 3: x and y are differ ent value ) scsy output sck output scsx output t scc v ol v oh v ol v ol v oh
document number: 002- 10635 rev.** page 203 of 247 s6j33 10/20/30/40 series preliminar (8) serial chip select used (scscr:csen=1) ? serial clock output signal detect level "l" (smr, scsfr:scinv=1) ? serial chip select inactive level "l" (scscr, scsfr:cslvl=0) (ta: recommended operating conditions, vcc3=3.3 v 0.3v%, vcc5=dvcc=5.0 v 10% /3.3v 0.3v, vcc53=5.0 v 10% / 3.3 v 0.3v, v ss =dv ss =0.0 v, v cc 12=1. 15v 0. 06v ) parameter symbol pin name condition s value unit remarks min max scs sck setup time t cssi sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12, sck16 to sck17 scs0x, scs1x, scs2x_1, scs3x_1, scs4, scs8x to scs12x, scs16x to scs17x mode (cl= 2 0 pf, i ol = -5 ma, i oh = 5 ma) t cssu *1 -15 - ns sck scs hold time t cshi t cshd *2 +0 - ns scs deselect time t csdi scs0x, scs1x, scs2x_1, scs3x_1, scs4, scs8x to scs12x csds *3 -15 +5t clk_lcpna *4 - ns scs16x to scs17x t csds *3 - /23 - ns scs sck setup cssi sck2_0, sck3_0, scs2x_0, scs3x_0 master mode (cl = 20pf, i ol = - 10ma, i oh =10ma) t cssu *1 -10 - ns sck scs hold time cshi t cshd *2 +0 - ns scs deselect time csdi scs2x_0, scs3x_0 t csds *3 - //3q - ns scs sck setup time t csse sck0 to sck4, sck8 to sck12 scs0x to scs4x, scs8x to scs12x mode (cl= 2 0 pf, i ol = -5 ma, i oh = 5 ma) 4 t clk_lcpna *4 + 15 - ns sck16 to sck17, scs16x to scs17x 4 clk_comp + - ns sck scs hold time t cshe sck0 to sck4, sck8 to sck12, sck16 to sck17, scs0x to scs4x, scs8x to scs12x, scs16x to scs17x 0 - ns scs deselect time t csde scs0x to scs4x, scs8x to scs12x 4 clk_lcpna *4 + 15 - ns scs16x to scs17x 4 clk_comp +1 5 - ns scs sot delay time scs0x to scs4x, scs8x to scs12x, scs16x to scs17x, sot0 to sot4, sot8 to sot12, sot16 to sot17 40 ns scs sot delay time t dee 0 - ns
document number: 002- 10635 rev.** page 204 of 247 s6j33 10/20/30/40 series preliminar parameter symbol pin name condition s value unit remarks min max sck scs clock switching time t scc sck0, sck1, sck2_1, sck3_1, sck4, sck8 to sck12, scs0x, scs1x, scs2x_1, scs3x_1, scs4, scs8x to scs12x mode round operation (cl= 2 0 pf, i ol = -5 ma, i oh = 5 ma) 4 t clk_lcpna *4 + 0 4 t clk_lcpna * 4 +15 ns sck16 to sck17, scs16x to scs17x 4 t clk_comp +0 4 clk_comp ns sck2_0, sck3_0, scs2x_0, scs3x_0 master mode round operation (cl = 20pf, i ol = - 10ma, i oh =10ma) 4 t clk_lcpna *4 +0 4 t clk_lcpna * 4 +10 ns *1: t cssu =scstr:cssu[7:0] x serial chip select timing operating clock *2: t cshd =scstr:cshd[7:0] x serial chip select timing operating clock *3: t csds =scstr:csds[15:0] x serial chip select timing operating clock for details on *1 , *2 , and *3 above, see the hardware manual. *4 t clk_lcpna n=0:ch.0 to ch.4, n=1:ch.8 to ch.12 otes ? this is the ac characteristic in clk synchronized mode. ? cl is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by the internal operating clock used and other parameters. for details, see the hardware manual.
document number: 002- 10635 rev.** page 205 of 247 s6j33 10/20/30/40 series preliminar master mode sck output sot (normal synchronous transfer) sot (spi compatible ) t cssi scs output t cshi t csdi v oh v oh v ol v ol v oh v ih slave mode sck input sot (normal synchronous transfer) sot (spi compatible ) t csse scs input t cshe t csde t dse t dee v ih v il v il v ol v ol v oh clock switching example by master mode round operation (x,y= 0, 1, 2, 3 : x and y are different value) scsy output sck output scsx output t scc v oh v oh
document number: 002- 10635 rev.** page 206 of 247 s6j33 10/20/30/40 series preliminar lin interface (v2.1) (lin communication control interface (v2.1)) timing (smr:md2 - 0=0b011) (1) external clock selected (bgr:ext=1) (t a : recommended operating conditions, vcc3=3.3 v 0.3v, vcc5=dvcc=5.0 v 10% /3.3 v 0.3v, vcc53=5.0 v 10% / 3.3 v 0.3v, v ss =dv ss =0.0 v, v cc 12=1. 15v 0. 06v ) parameter symbol pin name conditions value unit remarks min max serial clock "l" pulse width t slsh sck0 to sck4, sck8 to sck12 - t clk_lcpna *1 +10 - ns sck16 to sck17 t clk_comp +10 - ns serial clock "h" pulse width t shsl sck0 to sck4, sck8 to sck12 t clk_lcpna *1 +10 - ns sck16 to sck17 t clk_comp +10 - ns sck falling time t f sck0 to sck4, sck8 to sck12, sck16 to sck17 - 5 ns sck rising time t r - 5 ns *1: n=0:ch.0 to ch.4, n=1:ch.8 to ch.12 external clock selected sck t shsl v il
document number: 002- 10635 rev.** page 207 of 247 s6j33 10/20/30/40 series preliminar i 2 c timing (smr:md2 - 0=0b100) (t a : recommended operating conditions, vcc5=vcc53=5.0 v 10%, v cc 12=1. 15v 0. 06v , v ss =0.0 v) parameter symbol pin name condition s standard mode high - speed mode unit remarks min max min max scl clock frequency f scl scl0, scl1, scl4, scl8 to scl12, scl16 to scl17 c l =50pf, r=(vp/i ol ) * 1 0 100 0 400 khz repeat "start" condition hold time 66/ t hdsta sda0, sda1, sda4 sda8 to sda12, sda16 to sda17, scl0, scl1, scl4, scl8 to scl12, scl16 to scl17 4.0 - 0.6 - s period of "l" for scl clock t low scl0, scl1, scl4, scl8 to scl12, scl16 to scl17 4.7 - 1.3 - s period of "h" for scl clock t high 4.0 - 0.6 - s repeat "start" condition setup time scl sda susta sda0, sda1, sda4 sda8 to sda12, sda16 to sda17, scl0, scl1, scl4, scl8 to scl12, scl16 to scl17 4.7 - 0.6 - s data hold time scl sda t hddat 0 3.45 *2 0 0.9 *3 s data setup time sda scl t sudat 250 - 100 - ns "stop" condition setup time scl sda susto 4.0 - 0.6 - s bus free time between "stop" condition and "start" condition buf - 4.7 - 1.3 - s noise filter t sp - t nft *4 - t nft *4 - ns notes: only ch.16 and ch.17 are standard mode/high - speed mode correspondence. in ch.0, ch.1, ch.4, and ch.8 to ch.12, only a standard mode is correspondence. *1: r and c l represent the pull - up resistance and load capacitance of the scl and sda output lines, respectively. vp shows that the power - supply voltage of the pull - up resistor and i ol shows the v ol guarante e current. *2: the maximum t hddat only has to be met if the device does not extend the "l" width (t low ) of the scl signal. *3: a high - speed mode i 2 c bus device can be used on a standard mode i 2 c bus system as long as the device satisfies the requirement of "t sudat 250 ns". *4: t nft =(nfcr:nft[4:0]+1) x 2 x t clk_lcp0a (ch.0, ch.1, ch4) t nft =(nfcr:nft[4:0]+1) x 2 x t clk_lcp1a (ch.8 to ch.12) t nft =(nfcr:nft[4:0]+1) x 2 x t clk_comp (ch.16 to ch.17)
document number: 002- 10635 rev.** page 208 of 247 s6j33 10/20/30/40 series preliminar sda scl t hdsta t low t hddat t sudat t high t susta t hdsta t sp t buf t susto
document number: 002- 10635 rev.** page 209 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.7 timer input (t a : recommended operating conditions, vcc3=3.3 v 0.3v, vcc5=dvcc=5.0 v 10%, vcc53=5.0 v 10% / 3.3 v 0.3v, v ss =dv ss =0.0 v, v cc 12=1. 15v 0. 06v ) parameter symbol pin name condition s value unit remarks min max input pulse width t twh , t twl ppg0_tin1 to ppg31_tin1 - 4t clk_lcpna * 1 - ns 4t clk_lcpna *1 ns 4t clk_lcpna *1 ns ,,,, ,, ,, icu0_in1 to icu2_in1, icu8_in1 to icu10_in1 - 4t clk_lcpna * 2 - ns 4t clk_lcpna *2 100 ns 100 4t clk_lcpna *2 <100 ns frt0_text to frt4_text, frt8_text to frt10_text - 4t clk_lcpna * 3 - ns 4t clk_lcpna *3 100 ns 100 4t clk_lcpna *3 ns ,, tin16 to tin17 - 4t clk_lcpna * 4 - ns 4t clk_lcpna *4 ns 4t clk_lcpna *4 ns ,, - 4t clk_comp - ns 4t clk_comp ns 4t clk_comp ns q qlqlqlqlq qlql *2: n=0:unit.0 to unit.2, n=1:unit.8 to unit.10 *3: n=0:ch.0 to ch.4, n=1:ch.8 to ch.10 *4: n=0:ch.0 to ch.1, n=1:ch.16 to ch.17 ? timer input timing v ih v il icu x _ in 0/1 tiwl tiwh v ih v il frtx_ text tinx ppg x _ in 1
document number: 002- 10635 rev.** page 210 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.8 qprc timing (t a : recommended operating conditions, vcc3=3.3 v 0.3v, vcc5=dvcc=5.0 v 10%, vcc53=5.0 v 10% / 3.3 v 0.3v, v ss =dv ss =0.0 v, v cc 12=1. 15v 0. 06v ) parameter symbol pin name conditions value unit remarks min max ain pin "h" width t ahl ain8 to ain9 - 4t clk_lcp1 a - ns 4t clk_lcp1 a 100 ns ain pin "l" width all ain8 to ain9 bin pin "h" width bhl bin8 to bin9 bin pin "l" width bll bin8 to bin9 time from ain pin "h" level to bin rise t aubu ain8 to ain9, bin8 to bin9 pc_mode2 or pc_mode3 time from bin pin "h" level to ain fall t buad ain8 to ain9, bin8 to bin9 pc_mode2 or pc_mode3 time from ain pin "l" level to bin fall t adbd ain8 to ain9, bin8 to bin9 pc_mode2 or pc_mode3 time from bin pin "l" level to ain rise t bdau ain8 to ain9, bin8 to bin9 pc_mode2 or pc_mode3 time from bin pin "h" level to ain rise t buau ain8 to ain9, bin8 to bin9 pc_mode2 or pc_mode3 time from ain pin "h" level to bin fall t aubd ain8 to ain9, bin8 to bin9 pc_mode2 or pc_mode3 time from bin pin "l" level to ain fall t bdad ain8 to ain9, bin8 to bin9 pc_mode2 or pc_mode3 time from ain pin "l" level to bin rise t adbu ain8 to ain9, bin8 to bin9 pc_mode2 or pc_mode3 zin pin "h" width zhl zin8 to zin9 qcr:cgsc="0" zin pin "l" width zin8 to zin9 qcr:cgsc="0" time from determined zin level to ain/bin rise and fall t zabe ain8 to ain9, bin8 to bin9, zin8 to zin9 qcr:cgsc="1" time from ain/bin rise and fall time to determined zin level t abez ain8 to ain9, bin8 to bin9, zin8 to zin9 qcr:cgsc="1"
document number: 002- 10635 rev.** page 211 of 247 s6j33 10/20/30/40 series preliminar ain bin t aubu t buad t adbd t bdau t ahl t all t bhl t bll bin t buau t aubd t bdad t adbu t bhl t bll t ahl t all ain
document number: 002- 10635 rev.** page 212 of 247 s6j33 10/20/30/40 series preliminar t zhl t zll t zabe t abez zin ain/bin zin
document number: 002- 10635 rev.** page 213 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.9 trigger input (t a : recommended operating conditions, vcc3=3.3 v 0.3v, vcc5=dvcc=5.0 v 10%, vcc53=5.0 v 10% / 3.3 v 0.3v, v ss =dv ss =0.0 v, v cc 12=1. 15v 0. 06v ) parameter symbol pin name condition s value unit remarks min max input pulse width t trgh , t trgl eint0 to eint23 100 adtrg0 to adtrg1 5t clk_lcp1a 5t clk_lcp1a 100 ns 100 5t clk_lcp1a <100 ns eint0 to eint23 1 s stop mode ? trigger input timing v ih v il intx trgl trgh v ih v il adtrg x
document number: 002- 10635 rev.** page 214 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.10 nmi input (t a : recommended operating conditions, vcc5=5.0 v 10%, v ss =0.0 v) parameter symbol pin name conditions value unit remarks min max input pulse width t nmil nmix - 300 - ns ? nmix input timing v ih nmix n mil v ih v il v il
document number: 002- 10635 rev.** page 215 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.11 low voltage detection (external voltage) low - voltage detection (external low - voltage detection) (t a : recommended operating conditions, v ss =av ss =0.0 v) parameter symbol pin name conditions value unit remarks min typ max supply voltage range v dp5 vcc5 - 3.5 *3 5.5 *3 v 2.7 *4 - 3.6 *4 detection voltage (before trimming) v dlbt vcc5 *1 3.6 *3 4.0 *3 4.4 *3 v when power - supply voltage falls and detection level is set initially 2.3 *4 2.6 *4 2.9 *4 vcc3 *1 2.3 2. 6 2.9 v detection voltage (after trimming) v dlat vcc5 *1 3.86 *3 4.0 *3 4.14 *3 v when power - supply voltage falls and detection level is set initially typ3.5% 2.51 *4 2.6 *4 2.69 *4 vcc3 *1 2.51 2.6 2.69 v hysteresis width v hys vcc5 - - 100 - mv when power - supply voltage rises /z - yd gflql g - - - - 30 s power supply voltage regulation vcc5 - -2 - 2 v/ms *2 *1: if the fluctuation of the power supply is faster than the low - voltage detection time, there is a possibility to generate or release after the power supply voltage has exceeded the detection voltage range. *2: please suppress the change of the power supply within the range of the power - supply voltage regulation to do a low - voltage detection by detecting voltage (vdl) *3: for s6j33xxxs b or s6j33xx xu b or s6j33xxx tb or s6j33xxx vb option. *4: for s6j33xxxa b or s6j33xxxb b or s6j33xxxc b or s6j33xxxd b or s6j33xxx eb or s6j33xxx fb or s6j 33xxx gb or s6j33xxx hb option. ote s ? the detection/release threshold values of following lvd channels are potentially belo w supply range defined in 9.1.2 recommended operating condition . lvdh1 (vcc5) lvdh2 (vcc3) ? please use these lvd channels with your own risk. ? please monitor t he external power supplies on the pcb if needed. ? for s6j33xxxsb or s6j33xxxub or s6j33xxxtb or s6j33xxxvb options: depending on the threshold setting, lvdh1 can always detect vcc5 low voltage before the supply drops b elow the level defined in 9.1.2 recommended operating condition. please refer to product hardware manual for available list of lvdh1 threshold settings.
document number: 002- 10635 rev.** page 216 of 247 s6j33 10/20/30/40 series preliminar low - voltage detection (1. 15 v power supply low - voltage detection) (t a : recommended operating conditions, v ss =av ss =0.0 v) parameter symbol pin name conditions value unit remarks min typ max supply voltage range v rdp12 vcc12 - 1. 09 - 1.21 v detection voltage (before trimming) * v rdlbt vcc12 *1 0.7125 0.8125 0.9125 v when power - supply voltage falls flqyd (after trimming) v rdlat vcc12 *1 0.784 0.8125 0.841 v when power - supply voltage falls typ3.5% 0.888 0.95 0.984 hysteresis width v rhys - - - 75 - mv when power - supply voltage rises /z - yd gflql g - - - - 30 s *1: if the power fluctuation time is less than the low - voltage detection time (trd) and has passed the detection voltage range, the detection may occur or be canceled after the supply voltage has passed the detection voltage range. ote s ? the detection/release threshold values of lvd l2 channel is potentially belo w supply range defined in 9.1.2 recommended operating condition . ? please use this lvd l2 channel with your own risk. ? please monitor the external power supplies on the pcb if needed.
document number: 002- 10635 rev.** page 217 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.12 low voltage detection (internal voltage) low - voltage detection (internal low - voltage detection for lvdl0) (t a : recommended operating conditions, v ss =av ss =0.0 v) parameter symbol pin name conditions value unit remarks min typ max supply voltage range v rdp5 - - 1.05 - 1.21 v detection voltage v rdl - *1 0.75 0.85 0.95 v when power - supply voltage falls lzlg v rhys - - - 100 - mv when power - supply voltage rises /z - yd gflql g - - - - 30 s *1: if the power fluctuation time is less than the low - voltage detection time (trd) and has passed the detection voltage range, the detection may occur or be canceled after the supply voltage has passed the detection voltage range. ote s ? the detection/release threshold values of lvd l0 channel is potentially belo w supply range defined in 9.1.2 recommended operating condition . low - voltage detection (internal low - voltage detection for lvdl1) (t a : recommended operating conditions, v ss =av ss =0.0 v) p arameter symbol pin name conditions value unit remarks min typ max supply voltage range v rdp5 - - 1.05 - 1.21 v detection voltage (before trimming) v rdlbt - *1 0.775 0.875 0.975 v when power - supply voltage falls flqyd (after trimming) v rdlat - *1 0.844 0.875 0.906 v when power - supply voltage falls typ3.5% hysteresis width v rhys - - - 75 - mv when power - supply voltage rises /z - yd gflql g - - - - 30 s *1: if the power fluctuation time is less than the low - voltage detection time (trd) and has passed the detection voltage range, the detection may occur or be canceled after the supply voltage has passed the detection voltage range. ote s ? the detection/release threshold values of lvd l1 channel is potentially belo w supply range defined in 9.1.2 recommended operating condition .
document number: 002- 10635 rev.** page 218 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.13 high current output slew rate (t a : recommended operating conditions, v cc 5,v cc 53,dv cc =5.0v 10%, v cc 3=3.3v 0.3v, v cc 12=1. 15v 0. 06v , v ss =dv ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max output rise / fall time t r2 ,t f2 p1_17 to p1_31, p2_00 to p2_08 - 15 - 100 ns load capacitance 85pf v h =v ol8 +0.9 x (v oh8 - v ol8 ) v l =v ol8 +0.1 x (v oh8 - v ol8 )
document number: 002- 10635 rev.** page 219 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.14 display controller (13 - 1) display controller0 timing (ttl mode) (t a : recommended operating conditions, vcc53=5.0 v 10%,3.3v 0.3v , v ss =dv ss =av ss =0.0 v) parameter symb ol pin name conditions value unit remarks min max clock cycle t dc0cyc dsp0_clk (cl = 20pf, i ol = - 15ma, i oh =15ma), 25 - ns output delay from dsp0_clk |t dc0d | dsp0_r7 0 dsp0_g7 -0 dsp0_b7 -0 dsp0_en dsp0_hsync dsp0_vsync (cl = 20pf, iol= - 5ma, ioh=5ma) - 3.2 ns output data valid time t dc0v dsp0_r7 0 dsp0_g7 -0 dsp0_b7 -0 dsp0_en dsp0_hsync dsp0_vsync 21.8 - ns t dc0cyc - 3.3ns+0. 1ns otes tis is taret spec dsp0_clk v oh v oh dsp0_data0_11 - 0 dsp0_data1_11 - 0 dsp0_ctrl11 - 0 valid t dc 0d t dc 0v
document number: 002- 10635 rev.** page 220 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.15 external bus interface timing clock output timing (ta: recommended operating conditions, vcc53=5.0 v 10%, v ss =0.0 v) (external load capacitance 16pf) parameter symbol pin name conditions value unit remarks min max cycle time t cyc mclk 2ma is selected in odr bit in ppc_pcfg r register. - ns flzlg t / / g t cyc - g t cyc ns fzzlg t clch mclk d l t cyc - 7 d l t cyc + 7 ns *1: if division - ratio is even value, dh is equivalent to 0.5. otherwise, dh is calculated as the following. dh = the number rounding "division - ratio x 0.5" down to the nearest integer / division - ratio division - ratio is multiplication value among sysdiv bit, hpmdiv bit and extbusdiv bit setting. ex). setting sysdiv to 1 - division, hpmdiv to 7 - division, extbusdiv to 1 - division, dh is calculated as 0.429. *2: if division - ratio is even value, dl is eq uivalent to 0.5. otherwise, dl is calculated as the following. dl = the number rounding "division - ratio x 0.5" up to the nearest integer / division- ratio division - ratio is multiplication value among sysdiv bit, hpmdiv bit and extbusdiv bit setting. ex). setting sysdiv to 1 - division, hpmdiv to 7 - division, extbusdiv to 1 - division, dl is calculated as 0.571. ? clock output timing
document number: 002- 10635 rev.** page 221 of 247 s6j33 10/20/30/40 series preliminar common timing betw een read and write (ta: recommended operating conditions, vcc53=5.0 v 10%, v ss =0.0 v) (external load capacitance 16pf) parameter symbol pin name conditions value unit remarks min max cycle time (without mrdy) t cyc mclk 2ma is selected in odr bit in ppc_pcfgr register. 62.5 - ns cycle time (with mrdy) t cyc mclk 62.5 - ns if using mrdy, set mclk to 20mhz or less. 6gdl t cso mclk, mcsx0 to mcsx3 0.5 18 ns address delay ao mclk, mad00 to mad23 0.5 18 ns rdy setup time rdys mclk, mrdy "cmos schmitt input" and "disable noise filter" are selected in ppc_pcfgr register. - ns gl t rdyh mclk, mrdy 0 - ns otes tis is taret spec ? external bus i/f common timing ?
document number: 002- 10635 rev.** page 222 of 247 s6j33 10/20/30/40 series preliminar read timing (ta: recommended operating conditions, vcc53=5.0 v 10%, v ss =0.0 v) (external load capacitance 16pf) parameter symbol pin name conditions value unit remarks min max data setup time t dsr moex, mdata00 to mdata15 266fl lqsdqglde qlld fglq ppc_pcfgr register. cy c - ns data hold time t dhr moex, mdata00 to mdata15 - ns moex delay time t rdo mclk, moex 2ma is selected in odr bit in ppc_pcfgr register. 18 ns otes tis is taret spec ? external bus i/f read timing ?
document number: 002- 10635 rev.** page 223 of 247 s6j33 10/20/30/40 series preliminar write timing (ta: recommended operating conditions, vcc53=5.0 v 10%, v ss =0.0 v) (external load capacitance 16pf) parameter symbol pin name conditions value unit remarks min max mwex delay time t weo mclk, mwex 2ma is selected in odr bit in ppc_pcfgr register. 0.5 18 byte mask delay time t wro mclk, mdqm0 to mdqm1 18 ns data delay time t do mclk, mdata00 to mdata15 18 ns data delay time (hi - z output) t doz mclk, mdata00 to mdata15 - 18 ns otes tis is taret spec ? external bus i/f write timing ?
document number: 002- 10635 rev.** page 224 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.16 ddr- hsspi (16 - 1) ddr - hsspi interface timing (sdr mode) (t a : recommended operating conditions, vcc3=3.3 v 0.3 v, v ss =dv ss =av ss =0.0 v) parameter symbol pin name conditions value unit remarks min max hsspi clock cycle t cyc m_sclk0 (cl = 20pf, i ol = - 10ma, i oh =10ma), 10 m_sclk delayed sample clock t spcnt - 0 tcyc ns m_sd ata > delayed sample clock input setup time isdata m_sdata0_0 -3 m_sdata1_0 -3 3.5 - ns delayed sample clock -> m_ sdata input hold time ihdata m_sdata0_0 -3 m_sdata1_0 -3 2.0 - ns m_sclk m_sd ata output delay time oddata m_sdata0_0 -3 m_sdata1_0 -3 - 6.5 ns t cyc - 3.5ns m_sclk m_sd ata output hold time ohdata m_sdata0_0 -3 m_sdata1_0 -3 3.5 - ns m_sclk > m_ssel output delay time odsel m_ssel0, 1 - 5.5 ns t cyc - 4.5ns m_sclk > m_ssel output hold time ohsel m_ssel0, 1 4.5 - ns otes tis is taret spec t cyc v ih v il g_sclk 0 g _ s d ata 0 _ 0 -3 , g _ s d ata 1 _ 0 -3 (input timing) v oh v oh v ih v il valid t isdata delayed sample clock t ihdata v oh t spcnt v oh v ol g _ s d ata 0 _ 0 -3 , g _ s d ata 1 _ 0 -3 (output timing) v oh v ol valid t oddata t ohdata v oh v ol gssel 0 , 1 (output timing) v oh v ol valid t odsel t ohsel m_sdata0_0 - 3, m_sdata1_0 - 3 m_sdata0_0 - 3, m_sdata1_0 - 3 m_sclk0 m_ssel0,1
document number: 002- 10635 rev.** page 225 of 247 s6j33 10/20/30/40 series preliminar (16 - 2) ddr - hsspi interface timing (ddr mode) (t a : recommended operating conditions, vcc3=3.3 v 0.3 v, v ss =dv ss =av ss =0.0 v) parameter symb ol pin name conditions value unit remarks min max hsspi clock cycle t cyc m_sclk0 (cl = 20pf, i ol = - 10ma, i oh =10ma), 10 m_sclk delayed sample clock t spcnt 0 tcyc ns m_sd ata > delayed sample clock input setup time isdata m_sdata0_0 -3 m_sdata1_0 -3 1.0 - ns delayed sample clock - > m_sdata input hold time t ihdata m_sdata0_0 -3 m_sdata1_0 -3 1.0 - ns m_sclk m_sd ata output delay time oddata m_sdata0_0 -3 m_sdata1_0 -3 - 3.5 ns t cyc /2 - 1.5n s m_sclk m_sd ata output hold time ohdata m_sdata0_0 -3 m_sdata1_0 -3 1.5 - ns m_sclk m_ssel output delay time odsel m_ssel0, 1 - 7.0 ns t cyc - 3.0ns m_sclk m_ssel output hold time ohsel m_ssel0, 1 3.0 - ns otes tis is taret spec v oh v ol v oh v ol v oh v ol v oh v ol t cyc v ih v il g_sclk 0 g _ s d ata 0 _ 0 -3 , g _ s d ata 1 _ 0 -3 (input timing) v oh v oh v ih v il valid t isdata delayed sample clock t ihdata v oh t spcnt g _ s d ata 0 _ 0 -3 , g _ s d ata 1 _ 0 -3 (output timing) valid t oddata gssel 0 , 1 (output timing) valid t odsel t ohsel valid v ol t ohdata t oddata t ohdata m_sdata0_0 m_sdata1_0 m_sdata0_0 m_sdata1_0 m_sclk0 m_ssel0,1
document number: 002- 10635 rev.** page 226 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.17 hyper bus (16 - 1) hyper bus write timing (hyperflash) (t a : recommended operating conditions, vcc3=3.3 v 0.3v, v ss =dv ss =av ss =0.0 v) parameter symb ol pin name conditions value unit remarks min max hyper bus clock cycle t ckcyc m_ck (cl = 20pf, i ol = - 10ma, i oh =10ma), 10.0 - ns cs > ck chip select setup time t css m_cs#_1,2 3.0 - ns dq - > ck input setup time t is m_dq7 -0 1.25 - ns ck input hold time t ih m_dq7 -0 1.25 - ns ck > cs chip select hold time t csh m_cs#_1,2 0 - ns otes tis is taret spec v ih v oh t css v ol v il ca0 47-40 ca0 3- 32 ca1 31-24 ca1 23-1 ca2 15- ca2 7-0 dn 15- dn 7-0 v ol t dsv t cshi t is t dsz v oh t css t csh t ih t ckcyc g_ck m_ck g_rwds m_rwds g_dq 7 ~ 0 m_dq 7 ~ 0 g_cs#_ 1 , 2 m_cs#_ 1 , 2
document number: 002- 10635 rev.** page 227 of 247 s6j33 10/20/30/40 series preliminar (16 - 2) hyper bus write timing (hyperram) (t a : recommended operating conditions, vcc3=3.3 v 0.3v, v ss =dv ss =av ss =0.0 v) parameter symb ol pin name conditions value unit remarks min max hyper bus clock cycle t ckcyc m_ck (cl = 20pf, i ol = - 10ma, i oh =10ma), 10.0 - ns cs > ck chip select setup time t css m_cs#_1,2 3.0 - ns dq - > ck input setup time is m_dq7 -0 1.25 - ns ck input hold time ih m_dq7 -0 1.25 - ns ck > cs chip select hold time csh m_cs#_1,2 0 - ns rwds > ck data mask valid dmv m_rwds 0 - ns ck rwds refresh indicator valid t riv m_rwds - 6 ns ck > rwds(hi z) refresh indicator hold t rih m_rwds 0 - ns otes tis is taret spec v ih v oh t css v il v il ca0 47-40 ca0 39- 32 ca1 31-24 ca1 23-16 ca2 15-8 ca2 7-0 dn 15-8 dn 7-0 v ol t rih t riv t cshi t csm t po t rwr t is t ih t ih t is t dmv v ih v oh v ol t css t csh t ckcyc g_ck m_ck g_rwds m_rwds g_dq 7 ~ 0 m_dq 7 ~ 0 g_cs#_ 1 , 2 m_cs#_ 1 , 2
document number: 002- 10635 rev.** page 228 of 247 s6j33 10/20/30/40 series preliminar (16 - 3) hyper bus read timing (hyperflash) (t a : recommended operating conditions, vcc3=3.3 v 3.3v, v ss =dv ss =av ss =0.0 v) parameter symb ol pin name conditions value unit remarks min max hyper bus clock cycle t rdscyc m_ck (cl = 20pf, i ol = - 10ma, i oh =10ma), 10.0 - ns cs > ck chip select setup time t css m_cs#_1,2 3.0 - ns dq - > ck input setup is m_dq7 -0 1.25 - ns ck input hold time ih m_dq7 -0 1.25 - ns ck > cs chip select hold time csh m_cs#_1,2 0 - ns rds> dq (valid) rds transition to dq valid t dss m_dq7 -0 - 0.8 +0.8 ns rds> dq (invalid) rds transition to dq invalid t dsh m_dq7 -0 - 0.8 +0.8 ns otes tis is taret spec v ih g_ck m_ck v oh t css v ol v il g_rwds m_rwds g_dq 7 ~ 0 m_dq 7 ~ 0 ca0 47-40 ca0 39- 32 ca1 31-24 ca1 23-16 ca2 15-8 ca2 7-0 dn 15-8 dn 7-0 v ol t dsv t cshi t acc t ih t dsh t dqlz v oh v oh t css t csh g_cs#_ 1 , 2 m_cs#_ 1 , 2 dn+1 15-8 dn+1 7-0 t is t dss t oz t dsz t ckds t rdscyc v oh v ol
document number: 002- 10635 rev.** page 229 of 247 s6j33 10/20/30/40 series preliminar (16 - 4) hyper bus read timing (hyperram) (t a : recommended operating conditions, vcc3=3.3 v 0.3v, v ss =dv ss =av ss =0.0 v) parameter symb ol pin name conditions value unit remarks min max hyper bus clock cycle t rdscyc m_ck (cl = 20pf, i ol = - 10ma, i oh =10ma), 10.0 - ns cs > ck chip select setup time t css m_cs#_1,2 3.0 - ns dq - > ck input setup time is m_dq7 -0 1.25 - ns ck input hold time ih m_dq7 -0 1.25 - ns ck > cs chip select hold time csh m_cs#_1,2 0 - ns rwds> dq (valid) rwds transition to dq valid t dss m_dq7 -0 - 0.8 +0.8 ns rwds> dq (invalid) rwds transition to dq invalid t dsh m_dq7 -0 - 0.8 +0.8 ns ck > rwds refresh indicator valid t riv m_rwds - 6 ns ck > rwds(hi z) refresh indicator hold t rih m_rwds 0 - ns otes tis is taret spec v ih v oh t css v ol v il ca0 47-40 ca0 39- 32 ca1 31-24 ca1 23-16 ca2 15-8 ca2 7-0 dn 15-8 dn 7-0 v ol t rih t riv t cshi t csm t po t rwr t is t dsh t dqlz v oh v oh t css t csh dn+1 15-8 dn+1 7-0 t ih t dss t oz t dsz t ckds t rdscyc g_ck m_ck g_rwds m_rwds g_dq 7 ~ 0 m_dq 7 ~ 0 g_cs#_ 1 , 2 m_cs#_ 1 , 2 v oh v ol
document number: 002- 10635 rev.** page 230 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.18 ethernet avb (18 - 1) ethernet receive timing (t a : recommended operating conditions, vcc53=vcc3=3.3 v 0.3v, v ss =dv ss =av ss =0.0 v) parameter symb ol pin name conditions value unit remarks min max rxclk cycle t rxcyc rxclk - 40.0 rx setup time t rxs rxer rxdv rxd0 10.0 - ns t rxcyc -30ns rx hold time t rxh rxer rxdv rxd0 0 - ns - otes tis is taret spec t rxcyc rxclk v ih v ih valid v ih v il t rxs t rxh rxer rxdv rxd 0 -3
document number: 002- 10635 rev.** page 2 31 of 247 s6j33 10/20/30/40 series preliminar (18 - 2) ethernet transmit timing (t a : recommended operating conditions, vcc53=vcc3=3.3 v 0.3v, v ss =dv ss =av ss =0.0 v) parameter symb ol pin name conditions value unit remarks min max txclk cycle t txcyc txclk (cl = 20pf, iol= - 5ma, ioh=5ma), 40.0 col/crs input setup time crxs col crs 12.0 - ns - col/crs input hold crxh col crs 0.5 - ns - tx delay time t txd txer txen txd0 0.5 25 ns - otes tis is taret spec t txcyc txclk valid t crxs t crxh col crs valid v oh v ol txer txdv txd 0 -3 t txd t txd v ih v ih v ih v ih v ih v il
document number: 002- 10635 rev.** page 232 of 247 s6j33 10/20/30/40 series preliminar (18 - 3) mdio timing (t a : recommended operating conditions, vcc53=vcc3=3.3 v 0.3v, v ss =dv ss =av ss =0.0 v) parameter symb ol pin name conditions value unit remarks min max mdc cycle t mdcyc mdc (cl = 20pf, iol= - 5ma, ioh=5ma), 400.0 mdio input setup mdis mdio 100.0 - ns mdio input hold time mdih mdio 0.0 mdio output delay mdod mdio 10.0 190.0 ns otes tis is taret spec t mdcyc mdc v oh v oh v oh v ol valid v ih v il t mdis t mdih mdio (in) valid v oh v ol t mdod t mdod mdio (out) v oh txen
document number: 002- 10635 rev.** page 233 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.19 medialb (19 - 1) medialb input timing (t a : recommended operating conditions, vcc3=3.3 v 0.3v, v ss =dv ss =av ss =0.0 v) parameter symb ol pin name conditions value unit remarks min max mlbclk cycle t mckc mlbclk - 19.53 mlbsig, mlbdat input setup dsmcf mlbsig mlbdat 1.0 - ns mlbsig, mlbdat input hold dhmcf mlbsig mlbdat 0 - ns otes tis is taret spec (19 - 2) medialb output timing (t a : recommended operating conditions, vcc3=3.3 v 0.3v, v ss =dv ss =av ss =0.0 v) parameter symb ol pin name conditions value unit remarks min max mlbclk cy c le t mckc mlbclk (cl = 20pf, i ol = - 6ma, i oh =6ma), 19.53 mlbsig, mlbdat output stop mcfdz mlbsig mlbdat 10.73 - ns t mckc - q /6,/ sgd t dout mlbsig mlbdat 0 8.8 ns - otes tis is taret spec t mckc t dout v oh v ol mlbclk m l b d at, mlbsig v ih t mcfdz v ih v oh v ol valid input t mckc v i l t dsmcf v i h v i l mlbclk m lb d at, mlbsig v i h t dhmcf v i h v ih v il valid
document number: 002- 10635 rev.** page 234 of 247 s6j33 10/20/30/40 series preliminar 9.1.4.20 port noise filter (t a : recommended operating conditions, v cc 5,v cc 53,dv cc 5 =5.0v 10%, v ss =dv ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min max width for input removal - all gpio - - 17 ns ? * input pulse width less than at least 17nm is removed when port noise filter is enabled.
document number: 002- 10635 rev.** page 235 of 247 s6j33 10/20/30/40 series preliminar 9.1.5 a/d converter 9.1.5.1 electrical characteristics (t a : recommended operating conditions, v cc 5=5.0v 10%, v cc 12=1. 15v 0. 06v , v ss =av ss =0.0v) parameter symbol pin name conditions unit remarks min typ max resolution - - - - 12 bit ? total error - - - - 12 *6 lsb ? *3 - - 15 *7 lsb ? integral non linearity 4.0 lsb ? *4 differential non linearity 1.9 lsb ? *4 zero transition voltage v zt an0 to an63 / - /6 - avrl +12.5lsb *6 ? *5 avrl 14.5lsb *7 - avrl +15.5lsb *7 full - scale transition voltage v fst an0 to an63 - /6 - avrh +10.5lsb *6 avrh 16.5lsb *7 - avrh +13.5lsb *7 ? sampling time smp 0.3 s ? *1 compare time cmp - - 26 *1 a/d conversion time cnv 1. 1 s ? *1 resumption time 1 s ? analog port input current i ain an0 to an30, an32 to an38 1.0 - 1.0 a av ss ? v ain av cc 5 an31, an39 to an63 2.0 - 2.0 a analog input voltage v ain / - reference voltage avrh avrh5 4.5 *6 - 5.5 *6 v ? avcc 5 avrh 3.0 *7 - 3.6 *7 avrl avrl5/avss 0.0 v ? power supply current i a - 500 900(target) a ? 1unit i ah 1.0 200(target) a ? *2 i r avrh 5 - 1.0 3.5(target) *6 ma ? 1unit - 1.0 2.5(target) *7 ma ? 1unit i rh - - d *2 variation between channels - an0 to an 63 - - 4.0 lsb ? *1 : time per channel *2 : definition of the power supply current (when vcc 5 =avcc 5 =5.0 v) while the a/d converter is not operating and in stop mode *3 : total error is a comprehensive static error that includes the linearity after trimming by software. 1lsb=(avrh - avrl)/4096 *4 : 1lsb=(vfst - vzt)/4094 *5 : 1lsb=(avrh - avrl)/4096 *6: for s6j33xxxs b or s6j33xxxu b or s6j33xxx tb or s6j33xxx vb option. *7: for s6 j33xxxa b or s6j33xxxb b or s6j33xxxc b or s6j33xxxd b or s6 j33xxx eb or s6j33xxx fb or s6j33xxx gb or s6j33xxx hb option.
document number: 002- 10635 rev.** page 236 of 247 s6j33 10/20/30/40 series preliminar 9.1.5.2 notes on a/d converters about the output impedance of an external circuit for analog input when the external impedance is too high, the analog voltage sampling time may become insufficient. in this case, we recommend attaching a capacitor (about 0.1 f) to an analog input pin. analog input circuit model r c 12- bit a/d 3.9 kiloohms (max) 11.0 pf (max) (4.5 v a v cc 5 5.5 v) note: use the numerical values provided here simply as a guide. r c sampling on c omparator analog input
document number: 002- 10635 rev.** page 237 of 247 s6j33 10/20/30/40 series preliminar 9.1.5.3 glossary resolution: analog change that can be identified by an a/d converter integral linearity error: deviation of the straight line connecting the zero transition point ("0000 0000 0000" < -- > "0000 0000 0001") and full - scale transition point ("1111 1111 1110" < -- > "1111 1111 1111") from actual conversion characte ristics includes zero transition error, full - scale transition error, and non linearity error. differential linearity error: deviation from the ideal value of the input voltage required for changing the output code by 1 lsb total error : difference between the actual value and the theoretical value. the total error total error total error of digital output n = v nt - {1 lsb (n - 1) + 0.5lsb} [lsb] 1lsb 1lsb(ideal value) = avrh avrl [v] 4096 n: a/d converter digital output value. v zt (ideal value) = avrl + 0.5lsb[v] v fst (ideal value) = avrh - 1.5lsb[v] v nt : voltage at which the digital output changes from "(n 1)" to "n". fff ffe ffd 004 003 002 001 a v rl av r h {1 lsb (n - 1) + 0.5lsb } 1.5lsb v nt 0.5lsb ideal characteristics actual conversion characteristics ( actually - measured value) analog input actual conversion characteristics digital output
document number: 002- 10635 rev.** page 238 of 247 s6j33 10/20/30/40 series preliminar integral linearity error differential linearity error integral linearity error of digital output n = v nt - /6 - zt } [lsb] 1lsb differential linearity error of digital output n = v (n+1)t v nt 1 lsb [lsb] 1lsb 1lsb = v v [v] 4094 v zt : voltage for which digital output changes from "0x000" to "0x001" v : voltage for which digital output changes from "0xffe" to "0xfff". fff ffe ffd 004 003 002 001 a vrl av r h av r h actual conversion characteristics {1 lsb (n - 1) + v zt } n - 1 a vrl n - 2 n n + 1 v fst v nt v zt v (n+1)t v nt ideal characteristics actual conversion characteristics actual conversion characteristics actual conversion characteristics ideal characteristics digital output (measured value) (measured value) (measured value) (measured value) analog input analog input (measured value) digital output
document number: 002- 10635 rev.** page 239 of 247 s6j33 10/20/30/40 series preliminar 9.1.6 audio dac 9.1.6.1 electrical characteristics (t a : recommended operating conditions, av cc 3_dac=3.3v 0.3v, v cc 12=1. 15v 0. 06v , v ss =av ss =0.0v) parameter symbol pin name conditions *1 value unit remarks min typ max system clock frequency f clkda0 - - 2.048 - 18.43 mh z sampling clock fs 8 48 khz analog output load resistance *2 r l dac_l dac_r - 20 - - k - analog output load capacitance *2 c l - - - 100 pf - capacitance - c_l c_r 1.1 2.2 10 f - analog output single - end output range (full scale) dac_l dac_r rl=20k cl=100pf - 0.673 av cc 3_dac - v p - p - analog output voltage (zero) 0.5 av cc 3_dac v - thd+n *3 - - signal frequency: 1khz lpf(fc: 20khz) 82 -72 db - snr *3 signal frequency: 1khz lpf(fc: 20khz) a weighting filter 85 89 db dynamic range *3 - - 83 86 - db - out of band energy 20khz to 64fs db channel separation 80 db output impedance 150 200 250 psrr - - digital input: zero noise 50hz 35 - db - noise 1khz 50 - db - noise 20kh z - -40 - db - digital input :full 13 - db - supply current avcc3 _dac 2.2 3.2 ma - supply current power down avcc3 _dac 100 a - startup time *4 dae 650 *6 *1 : all parameters specified fs=44.1khz, system clock 256fs and 16 - bit data, rl- 20k, cl=100pf, unless otherwise noted. *2 : refer to notes *5 *3 : these values do not include the noise caused by the analog power supply. (refer to * 7. use examples) *4 : 2.2f i s connected to c_l, c_r. *5 : load connection r l is connected to avcc3_dac /2 (figure 9 .1). if r l is connected to ground, the coupling capacitance must be inserted as shown in (figure 9.3 )
document number: 002- 10635 rev.** page 240 of 247 s6j33 10/20/30/40 series preliminar dac macro lout/ rout r l : 20k c l : 100pf vavd / 2 (figure 9 .1) *6 : start up time time [ sec ] en [ v ] aouts [ v ] startup time 10 mv last voltage vdd 0 v 0 v (figure 9 .2) *start up time can be calculated as follows. 1.start up time(typ) = 650[ms] ( *4 ) 2.ccom=10uf(1/100) ccom is a capacitor connected to termial c_l/c_r including capacitance variance. =capacitance variance[%] 3.s tart up time = start up time(typ)(1) [ms] for example, ccom=2.42f then =(2.42f - 2.2f)/2.2f=10[%] so, start up time = 650ms 1+10/100 = 715[ms]
document number: 002- 10635 rev.** page 241 of 247 s6j33 10/20/30/40 series preliminar *7 use examples (figure 9 .3) otes ? c1 : more than 10f low esr capacitors ? c2 : 0.1f ceramic capacitors ? c3,c4 : 2.2f low esr capacitors ? impedance of each power line must be as low as possible. otes ? when dac is not used in your system, the related pins should be ? avcc3_dac=gnd and avss=gnd ? c_l=open and c_r=open ? dac_l=open and dac_r=open low noise regulator post lpf / buffer post lpf / buffer c1 c2 c3 c4 avcc3 dac av s s av s s av s s dac_r dac_l c_r c_l
document number: 002- 10635 rev.** page 242 of 247 s6j33 10/20/30/40 series preliminar 9.1.7 flash memory 9.1.7.1 electrical characteristics parameter rating unit remarks min typ max *3 sector erase time - 120 480 ms large sector*1 internal preprogramming time included 120 480 ms 8kb sector*1 internal preprogramming time included 120 480 ms 4kb sector *1 internal preprogramming time included 16bit write time( program ) - 30 384 s system - level overhead time excluded *1 32bit write time( program ) - 30 384 s system - level overhead time excluded *1 64bit write time( program ) 30 384 s level overhead time excluded *1 256bit write time( program ) 40 512 s level overhead time excluded *1 page mode write time( program ) 320 4096 s system - level overhead time excluded *1 32bit write time(work) - 30 384 s system - level overhead time excluded *1 erase count / ( program ) *3 years - - - temperature at write/erase time average temperature ta=+85 degrees celsius dfq data retention time (work) *3 1,000/20 10,000/1 0 years 100,000/ 5 years - - - temperature at write/erase time average temperature ta=+85 degrees celsius *1 : guaranteed value for up to 1,000 erases *2 : guaranteed value for up to 100,000 erases *3 : target value 9.1.7.2 notes while the flash memory is written or erased, shutdown of the external power (vcc5) is prohibited. in the application system where vcc5 might be shut down while writing or erasing, be sure to turn the power off by using an external voltage detection function. to put it concretely, after the external power supply voltage falls below the detection voltage (v dl ), hold vcc5 at 2.7v or more within the d uration calculated by the following expression: td *1 [s] + ( 1 / f crf *2 [mhz] ) x 1029 + 25 [s] *1: see " 9.1.4.11 low voltage detection (external voltage) " *2: see " 9.1.4.1 source clock timing "
document number: 002- 10635 rev.** page 243 of 247 s6j33 10/20/30/40 series preliminar 10. abbreviation a/d converter analog digital converter adc analog digital converter ahb advanced high performance bus ambatm advanced microcontroller bus architecture apb advanced peripheral bus atcm tcm a port axi advanced extensible interface b0tcm tcm b0 port b1tcm tcm b1 port bbu bit banding unit bdr boot description record btl bridge tied load can control are network cd clock domain cpu central processing unit cr cr oscillator crc cyclic redundancy check csv clock supervisor dac digital analog converter dap debug access port dual error detection dma dmac dma controller eam exclusive ecc error correction code embedded trace macro ext irc external interrupt controller fiq fast interrupt request fpu floating point unit frt free run timer gpio general purpose i/o hpm high performance matrix hw wdt hardware watchdog timer i/o input or output i2s inter ic sound icu input capture unit ipcu inter processor communication unit irc interrupt controller irq interrupt request isr interrupt service routine jtag joint test action group llpp low latency peripheral port lvd low voltage detector mcu microcontroller unit multi function serial interface nf noise filter nmi non maskable interrupt ocu output compare unit
document number: 002- 10635 rev.** page 244 of 247 s6j33 10/20/30/40 series preliminar osc oscillator pcm pulse coded module pll phase locked loop ponr power on reset ppc port pin configuration pss power saving state pwm pulse width modulation ram random access memory ric resource input configuration rom read only memory rtc real time clock rvd low voltage detection and reset for ram retention sct source clock timer sec single error correction secded single error correction and dual error detection she secure hardware extension smc stepper motor controller smix sound mixer sram static ram swfg sound waveform generator sw - wdt software watchdog timer sysc system controller tcflash flash connected to tcm tcm tightly coupled memory tcram ram connected to tcm tpu timing protection unit udc up - down counter vic vectored interrupt controller vram video ram wdr watchdog description record wdt watchdog timer wfg waveform generator workflash work flash memory
document number: 002- 10635 rev.** page 245 of 247 s6j33 10/20/30/40 series preliminar 11. ordering information part number package s6j331ekc b******* 208 pin plastic teqfp (teqfp208) s6j331ekb b******* 208 pin plastic teqfp (teqfp208) s6j331ek ab******* 208 teqfp (teqfp208) s6j331e j c b******* 176 pin plastic teqfp (teqfp176) s6j332ejc b******* 176 pin plastic teqfp (teqfp176) s6j331eja b******* 176 pin plastic teqfp (teqfp176) s6j332eja b******* 176 pin plastic teqfp (teqfp176) s6j332ehs b******* 144 plastic teqfp (teqfp144)
document number: 002- 10635 rev.** page 246 of 247 s6j33 10/20/30/40 series preliminar document history document title: S6J3310/s6j3320/s6j3330/s6j3340 series 32 - bit microcontroller spansion ? traveo tm family document number: 002- 10635 revision ecn orig. of change submission date description of change ** 5063970 tmor 0 3 / 0 4 /201 6 new spec.
document number: 002- 10635 rev.** march 4, 2016 page 247 of 247 s6j33 10/20/30/40 series preliminar sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/a rm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface lighting & power control cypress.co m/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com /touch usb controllers cypress.com/ usb wireless/rf cypress.com/wireless psoc? solutions cypress.com/psoc psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/support arm and cortex are the registered trademarks of arm limited in the eu and other countries. ? cypress semiconductor corporation 2016. this document is the property of cypress semiconductor corporation and its subsidia ries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellectual pro perty laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws a nd treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, t rademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwis e have a written agreement with cypress governing the use of the software, then cypress hereby grants you under its copyright rights in the software, a personal, non - exclusive, nontransferable license (without the right to sublicense) (a) for software prov ided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to di stribute the software in binary code form externally to end users (either directly or indir ectly through resellers and distributors), solely for use on cypress hardware product units. cypress also grants you a person al, non - exclusive, nontransferable, license (without the right to sublicense) under those claims of cypress's patents that are infr inged by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely to the minimum extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. any ot her use, reproduction, modification, translation, or compilation of the software is prohibited. cypress makes no warranty of any kind, express or implied, with regard to this document or any software, including, but not l imited to, the implied warranties o f merchantability and fitness for a particular purpose. cypress reserves the right to make changes to this document without f urther notice. cypress does not assume any liability arising out of the application or use of any product or circuit described in t his document. any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the f unctionality and safety of any application made of this information and any resulting product. cypress products are not designed, intended, or authorized for use as cri tical components in systems designed or intended for the operation of weapons, weapons s ystems, nuclear installations, life - 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